Author Archives: Marketing

DTIP 2015 – Montpellier – France, 27 – 30 April 2015

DTIP 2015 – Montpellier – France, 27 – 30 April 2015
DTIP

DTIP is a symposium including two main Conferences: the CAD, Design and Test Conference devoted to the development of Computer-Aided Design (CAD) tools and design methodologies for MEMS and MOEMS, and the Microfabrication, Integration and Packaging Conference dedicated to the development of integration technologies and packaging for MEMS and MOEMS. Both conferences share common plenary talks including invited talks, panels and special sessions to allow close interaction between both communities.

Among others, the program features presentations from Zeiss, ST, imec, ESIEE, Politechnico di Torino and Thales. A special session on « Co-design for MEMS based Smart Systems » is organized by Gerold Schröpfer from Coventor, France.

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Chips Are Going 3D, DRC Needs to Go 3D Too

SemiWiki
by Paul McLellan
covent1
The last paradigm shift in DRC was around 0.35um when designs got too large to handle as flat data, and hierarchical approaches were required. Back then the design rules themselves were not that complex, the explosion of data volume came from the complexity of the design itself. But each process node added more design rules intricacies and many new types of rules that needed to be checked.

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SPIE Advanced Lithography – February 22-26, 2015

spie-logo

SPIE Advanced Lithography, February 22-26, 2015, in San Jose, CA.

Coventor will attend SPIE 2015, visit us at booth #205

San Jose Marriott and San Jose Convention Center
San Jose, California, United States
22 – 26 February 2015

SPIE is a highly regarded exhibition for the industry’s top semiconductor suppliers, integrators, and manufacturers. 61 exhibiting companies in 2014.

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MEMS 2015 – January 18-22, 2015 – Estoril, Portugal

The 28th IEEE International Conference on Micro Electro Mechanical Systems

Coventor will attend MEMS 2015, visit us at booth #16.

ieee28

http://www.mems2015.org/

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Director, Semiconductor Process Integration and Modeling – Silicon Valley, CA

Director, Semiconductor Process Integration and Modeling – Silicon Valley, CA

We are seeking an MS- or PhD-level engineer who has substantial experience and expertise in semiconductor process integration and fabrication, and exceptional communication and presentation skills. You will work in partnership with Coventor’s CTO to promote acceptance and adoption of our unique virtual fabrication solutions at leading semiconductor companies worldwide. You will engage with industry leaders to solve critical manufacturing challenges for advanced technology nodes, including 14nm CMOS and beyond. You must be willing and able to do hands-on engineering with our software in order to provide effective leadership for our field engineers and valuable input to our software development team. Your compensation will be commensurate with your education and experience.

Education: Master’s degree required, PhD degree preferred, in related fields of Electrical Engineering, Chemical Engineering, Materials Science or Applied Physics.

Experience: You must have at least 8 years of work experience in the semiconductor industry with a focus semiconductor processing and integration.

Skills:  Semiconductor Processing, Semiconductor Device Physics (preferred), Computer-Aided Design (CAD) and Modeling, Python scripting language, JMP, Technical Writing, Communication and Presentation.

Location:  This position will ideally have a home base in Silicon Valley, CA, but we will consider other locations for highly qualified candidates. A substantial amount of customer-facing travel and time at customer sites in the US West and Asia is expected.

Coventor offers comprehensive benefits and is an EEO/AA Employer. You must be a current legal resident of the U.S. or have a valid U.S. visa to apply for this position. Please e-mail your cover letter and resume to job1822@coventor.com. Please indicate that this California-based Director position is of most interest to you.

Coventor Panel at IEDM Digs into Variation Issues

SemiWiki
by Tom Simon

Coventor Panel at IEDM Digs into Variation Issues
Recently I attended a panel discussion on variability in semiconductor fabrication hosted by Coventor in conjunction with the IEEE IEDM conference in San Francisco. The IEEE bills the conference as “the world’s pre-eminent forum for reporting technological breakthroughs in the areas of semiconductor and electronic device technology, design, manufacturing, physics, and modeling.” It’s easy to see how this discussion was relevant to the conference focus. SemiWiki’s own Dan Nenni was the panel moderator.
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Variation at IEDM

SemiWiki
by Paul McLellan

Variation at IEDM

IEDM (technically the International Electron Devices Meeting although I’ve never heard anyone use the full name) is in a couple of weeks time, in San Francisco. It is December 15-17th at the Hilton Union Square (which is not actually at Union Square but nearby at 333 O’Farrell Street).

For the last few years on the Tuesday evening Coventor have sponsored an event (with appetizers and drinks). Last year it was all about collaboration. This year the topic is variation, Survivor, Variation in the 3D Era. It is at the Hotel Nikko from 5.30pm to 8.30pm on Tuesday December 16th in the Carmel Room. Hotel Nikko is 222 Mason Street just around the corner from the Hilton.

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Survivor: Variation in the 3D Era – December 16, 2014 – San Francisco, CA

Location: “Carmel Room” at Hotel Nikko, San Francisco
Date: Tuesday, December 16, 2014
Time: 5:30pm -8:30pm (Cocktails and hors d’oeuvres)
6:00pm (Panel Begins)
RSVP by 12/10/14 RSVP-to-COVENTOR@coventor.com

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