Author Archives: Marketing

Comparing MEMS and the RMS Titanic: Some Thoughts from the IEEE MEMS 2018 Conference

By: Chris Welham, Sr. Manager, MEMS Applications Engineering

Conference dinner view of the life-size outlines of the Titanic and Olympic main deck’s, illuminated by blue light

How are MEMS and Large Ships Alike?

MEMS 2018 was held in Belfast, Northern Ireland this year, on the site where the RMS Titanic was built. On exhibit was the SS Nomadic, a tender used to transfer mail and passengers to the RMS Titanic and her sister ship RMS Olympic. Passing by the SS Nomadic on the way to the conference dinner, I noticed the riveted plates from which the tender was built. These riveted plates reminded me of the finite element plate models used in the MEMS+ module of CoventorMP, which can also be joined to other elements using “connectors” or “nodes” rather than rivets.

I wondered what other components in MEMS+ existed in the Titanic? For sure, perforated plates, or baffles. Many MEMS devices use perforated plates, either to aid the release etch in fabrication or for reasons of operation. Release etch, and the effects of pattern dependence, are key fabrication processes modeled in our virtual fabrication tool, SEMulator3D. A condenser microphone, which can be modeled using MEMS+, has at least one perforated back plate. Steel beams, too? Certainly, MEMS+ has Timoshenko Beam models, the underlying theory of which was first developed by Stephen Timoshenko just before the Titanic sank. Further comparison was harder. Comb capacitors? Well only as tuning condensers in the on-board Marconi Wireless Set, as it was then known. Fluid dampers? Perhaps in the engine supports of the SS Nomadic to reduce vibration.

What happened at the IEEE MEMS Conference?

Back to the conference, there was a wide range of interesting presentations and posters. Topics covered ranged from inertial sensors, actuators, acoustics, resonators and RF MEMS (all areas where we specialize), through to material science and microfluidics. It was good to see our tools being used to simulate a range of MEMS devices. We also had the opportunity to discuss emerging research in the area of MEMS simulation, which is always important for us to follow to ensure that our tools retain their leading edge capabilities.

What’s New with CoventorMP?

Incidentally, there are exciting new features for microphone design in the upcoming CoventorMP release, due out this Spring. We’re also expanding our capabilities for modeling suspension beams as well as lots of other new features. More to follow on these exciting enhancements as we get closer to the release date!

Future Outlook: The Advantages of Fully Depleted Silicon on Insulator (FD-SOI) Technology

By: Michael Hargrove, SP&I Engineer

If my memory serves me well, it was at the 1989 Device Research Conference where the potential merits of SOI (Silicon on Insulator) technology were discussed in a heated evening panel discussion. At that panel discussion, there were many advocates for SOI, as well as many naysayers. I didn’t really think more about SOI technology until the mid-nineties, when I was sitting in a meeting where the first SOI device data was being presented in the hallowed halls of IBM. The data was incredibly scattered and my thinking was “this technology is going nowhere!” The purported performance advantage was stated to be ~35%, simply due to the capacitance reduction (no longer did the bottom junction capacitance play a role) and the speed advantages of stacked devices in a NAND circuit. It all sounded great, but in the mid-nineties, the data simply didn’t support it. Nonetheless, the SOI advocates pursued their beloved technology, and the rest is history. SOI technology has been part of IBM’s main stream high-performance technology base through the 14nm node, including FinFETs on SOI. read more…

What the Experts Think: Delivering the Next 5 Years of Semiconductor Technology

Coventor recently sponsored an expert panel discussion at IEDM 2017 to discuss how we might advance the semiconductor industry into the next generation of technology.  The panel discussed alternative methods to solve fundamental problems of technology scaling, using advances in semiconductor architectures, patterning, metrology, advanced process control, variation reduction, co-optimization and new integration schemes.  Our panel included Rick Gottscho, CTO of Lam Research; Mark Dougherty, vice president of advanced module engineering at GlobalFoundries; David Shortt, technical fellow at KLA-Tencor; Gary Zhang, vice president of computational lithography products at ASML; and Shay Wolfling, CTO of Nova Measuring Instruments.

The Next 5 Years of Semiconductor Technology

L-R: Ed Sperling (moderator), Shay Wolfling, Rick Gottscho, Mark Dougherty, Gary Zhang, David Shortt

Here are a few expert predictions for the next 5 years of semiconductor technology that came out of the discussion:

FinFETs will get extended to at least to 5nm, and possibly 3nm

Rick Gottscho of Lam Research felt that FinFETs will get extended to at least 5nm, and possibly 3nm.    Shay Wolfing of Nova Measuring Instruments predicted that nanosheet technology could be used after FinFET extensions would not scale further.

EUV will be used at new nodes, followed by High NA Lithography

Gary Zhang of ASML stated that EUV will drive lithography at new nodes, with high-NA as an extension to EUV on the technology roadmap. Gary felt that managing the complexity and the cost of these new lithography techniques will be challenging, but feasible.

Materials and basic structures may diverge by supplier, at 7 nm and beyond

Mark Dougherty of GlobalFoundries noted that suppliers may not align at the end of the day on the same materials and basic structures to scale semiconductor technology. It’s possible that there might be some divergence, such as in back-end-of-line metallurgy.

Metrology can meet future technical challenges, but inspection and measurement costs may rise

Gary Zhang confirmed that 3D measurements below an angstrom are now possible, and that we have metrology solutions available for the near future.   David Shortt of KLA-Tencor asserted that end-to-end cycle time and cost are increasing for inspection and metrology, and that these trends may continue unless technical risk reduction is started early in the development process.

3D NAND technology will continue scaling beyond the existing 48 layer structures

Rick Gottscho stated that he sees a path over the next 10 years to scale 3D NAND manufacturing technology, up to 256 layers.   Rick had some concerns over film stress and challenging etch requirements in meeting this scaling projection.

If you are interested in reading more about this panel, you can find the first part of the panel transcript at Semiconductor Engineering.   Future articles in Semiconductor Engineering will highlight the remainder of the panel discussion, including the expert’s views on the role of advanced process control, variation reduction, co-optimization and new integration schemes in delivering the next 5 years of semiconductor technology.

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Semiconductor Simulation Corporate Engineer – Waltham, MA.

Semiconductor Simulation Corporate Engineer – Waltham, MA

At Coventor Inc., we build innovative software products to solve semiconductor technology challenges. Our 3D modeling software is revolutionizing the way that semiconductor chips are fabricated around the world. Enabled by our core intellectual property – an accelerated 3D voxel modeling and visualization engine – our software is evolving fast as our business and customer base expands rapidly.

We are seeking a motivated, collaborative semiconductor simulation expert to be the internal expert on the behavior and simulation of semiconductor devices within the logic and memory semiconductor market. In this role you will have a unique opportunity to use your technical expertise to enable the roll-out of new device simulation software for leading semiconductor companies. You will use your expertise to collaborate with the software development group on the validity of the simulator and also create technical material to highlight the strengths and capabilities of the tools for our potential customers. You will be supported by our team of highly skilled, collaborative software engineers and semiconductor process and integration experts.

This is a technical position requiring an understanding of the physics governing cutting edge nanoscale device behavior in production today and in the near future such as FinFETs, nanowires, and 3D NAND flash.

Responsibilities:

  • Participate in the definition of product features and direction, in collaboration with the software engineering team
  • Contribute to software validation, product documentation, case studies, and technical publications
  • Work with the sales and marketing teams to launch and market new features
  • Educate the applications team on new product features

 

Required Qualifications (all of the following):

  • PhD in Electrical Engineering or equivalent
  • Deep understanding of semiconductor devices
  • 3+ years of professional experience in nanoscale device simulation for commercial production, particularly for logic and memory
  • Good verbal communication and writing skills

 

Desirable Qualifications (any of the following):

  • Professional experience in a software development organization
  • Professional experience in semiconductor process modeling
  • Working knowledge of MATLAB

 

This regular, full-time position is located in Waltham, MA. Coventor offers comprehensive benefits and is an EEO/AA Employer. You must be a current legal resident of the U.S. or have a valid U.S. visa to apply for this position. Please e-mail your resume to job1863@coventor.com.

About Coventor:

For more information about Coventor, our business, and our products, please visit us on
the web at http://www.coventor.com.

Semiconductor Process and Integration Engineer – South Korea

Semiconductor Process and Integration Engineer – South Korea

We are seeking a BS/MS/PhD-level engineer who has experience and expertise in semiconductor process integration and fabrication. You will work with leading semiconductor companies to implement our virtual fabrication solution for their most advanced development programs, including 10nm CMOS technology and beyond! You will collaborate with the Semiconductor Process & Integration team in the Office of the CTO, along with our highly skilled software development team, to create integration and modeling solutions for industry-critical manufacturing challenges. Our tight-knit team of creative engineers is critical in leading customers into the methodology of virtual fabrication.

This is a hands-on engineering position, requiring proficiency in full flow semiconductor process integration, as well as strong communication and presentation skills. Your title, level of responsibility, creative freedom and salary will be commensurate with your education and experience.

Location: South Korea. This position requires residency in South Korea with a substantial amount of time at customer sites in South Korea. Work is expected to be partly based at customer/partner sites. Travel is expected.

Required Qualifications:

Education: Bachelor’s degree required, Master’s degree preferred, in related fields of Electrical Engineering, Chemical Engineering, Materials Science or Applied Physics.

Experience: Semiconductor Technology and Processing education and experience is required. Relevant employment experience in the semiconductor industry is required.

Skills: Semiconductor Processing and Integration, Semiconductor Device Physics (preferred), Computer-Aided Design (CAD) and Modeling, Python scripting language, Technical Writing , Communication and Presentation.

If you are interested in this opportunity and you are authorized to work in South Korea, e-mail your cover letter and CV in English to job1826@coventor.com.

About Coventor:

Coventor, Inc. (www.coventor.com) is the global market leader in virtual fabrication solutions for semiconductor technologies and design automation solutions for microelectromechanical systems (MEMS). Coventor serves a worldwide customer base of integrated device manufacturers, independent foundries, equipment makers, and R&D organizations that develop semiconductor and MEMS technologies for consumer, automotive, aerospace, industrial, and defense uses. Coventor’s predictive modeling tools and expertise enable its customers to dramatically reduce silicon learning cycles, giving them a time-to-market advantage and reducing technology development costs. The company is headquartered in Cary, NC and has offices in Waltham, MA; Silicon Valley, CA; Tokyo, Japan; Hsinchu, Taiwan; and Paris, France.

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Lam Research Completes Acquisition of Coventor, a Leader in Simulation and Modeling Solutions

FOR IMMEDIATE RELEASE

Lam Research Completes Acquisition of Coventor, a Leader in Simulation and Modeling Solutions

FREMONT, CA — (Marketwired) – 8/31/17 – Lam Research Corporation (Nasdaq:LRCX), a global supplier of innovative wafer fabrication equipment and services to the semiconductor industry, today announced that it has completed the acquisition of Coventor, Inc., a leading provider of simulation and modeling solutions for semiconductor process technology, micro-electromechanical systems (MEMS), and the Internet of Things (IoT). The combination of Lam and Coventor supports Lam’s advanced process control vision and is expected to accelerate process integration simulation to increase the value of virtual processing, further enabling chipmakers to address some of their most significant technical challenges. read more…

CMOS Image Sensors (CIS): Past, Present & Future

By: Sofiane Guissi, Semiconductor Process & Integration Engineer, Coventor

Over the last decade, CMOS Image Sensor (CIS) technology has made impressive progress. Image sensor performance has dramatically improved over the years, and CIS technology has enjoyed great commercial success since the introduction of mobile phones using on-board cameras. Many people, including scientists and marketing specialists, predicted 15 years earlier that CMOS image sensors were going to completely displace CCD imaging devices, in the same way that CCD devices displaced video capture tubes during the mid-1980’s. Although CMOS has a strong position in imaging today, it has not totally displaced CCD devices. On the other hand, the drive into CMOS technology has drastically increased the overall imaging market. CMOS image sensors have not only created new product applications, but have also boosted the performance of CCD imaging devices as well. In this paper, we describe the state-of-the-art in CMOS image sensor technology and discuss future perspectives.

read more…

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AIM Photonics Welcomes Coventor as Newest Member

 

 

 

 

For Immediate Release: March 16, 2017

Contact:
Laura Magee (ESD) | laura.magee@esd.ny.gov | (716) 846-8239 | (800) 260-7313
ESD Press Office | PressOffice@esd.ny.gov | (800) 260-7313
Steve Ference (AIM) | sference@sunypoly.edu | 518-956-7319

CUS-Backed Initiative Taps Process Modeling Specialist to Enable Manufacturing of High-Yield, High-Performance Integrated Photonic Designs

Today’s Announcement Builds On Progress Of Finger Lakes Forward, The Region’s Award-Winning Strategic Plan To Generate Robust Economic Growth And Community Development

ROCHESTER, NY and CARY, NCThe American Institute for Manufacturing Integrated Photonics (AIM Photonics), a public-private partnership advancing the nation’s photonics manufacturing capabilities, and Coventor®, Inc., a semiconductor process modeling software company, today announced Coventor as the newest member of AIM Photonics. Coventor will provide access to its unique, physics-driven 3D modeling technology to improve the performance and manufacturability of complex, integrated photonic designs. read more…

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