Author Archives: Marketing

BEOL Barricades: Navigating Future Yield, Reliability and Cost Challenges

By: David Fried, Ph.D., Chief Technology Officer, Semiconductor

Figure 1. M2-V1 process flow after (a) M2-L1 lithography, (b) M2-L2 litho, (c) V1 partial etch, (d) BLok open and (e) CuBS.

Coventor recently assembled an expert panel at IEDM 2016, to discuss changes to BEOL process technology that would be needed to continue dimensional scaling to 7 nm and lower. We asked our panelists questions such as: read more…

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Coventor’s Technology Roundtable at IEDM 2016

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Coventor Spearheads Discussion on Navigating Future Semiconductor Yield, Reliability and Cost Challenges

CARY, NC– December 6, 2016 – Coventor®, Inc., the leading supplier of automated software solutions for semiconductor devices and micro-electromechanical systems (MEMS), is sponsoring an advanced semiconductor technology panel on Tuesday, December 6 in San Francisco, California at the 2016 IEDM Conference. The panel is entitled “BEOL Barricades: Navigating Future Semiconductor Yield, Reliability and Cost Challenges”.

The panel discussion will explore major questions in advanced semiconductor development, including: read more…

Coventor to Collaborate with MIT for Photonics Process Modeling

Coventor will offer expertise and tools to support MIT’s role in AIM Photonics

CARY, NC– November 15, 2016 – Coventor, a leading supplier of semiconductor process development tools, today announced that it will collaborate with the Massachusetts Institute of Technology (“MIT”) on silicon photonics process modeling. MIT is a key player in the AIM Photonics program, a federally funded, public-private partnership established to advance domestic capabilities in integrated photonic technology and strengthen high-tech U.S.-based manufacturing. Coventor will provide its SEMulator3D® process modeling platform to model the effect of process variation in the development of photonic integrated components. Integration of photonics with conventional CMOS technology is needed for next-generation scientific, industrial and consumer applications ranging from data communications to metrology to aerospace applications. read more…

Bringing Advanced Semiconductor Manufacturing Technologies to Higher Education

By: Jimmy Gu, Ph.D., Semiconductor Process & Integration Engineer, Coventor

Campus image for November 2016 blog

Universities and other institutions of higher learning play a key role in developing our next generation of semiconductor technologies. Along with the theory of semiconductor technology, our next generation of scientists and engineers must learn about the practical methods used to design and manufacture the latest generation of semiconductor products. read more…

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Registration for Worldwide MEMS Design Contest Opens

MEMS Design contest company header image

Registration for Worldwide MEMS Design Contest Opens

Cadence, X-FAB, Coventor and Reutlingen University offering a first prize of $5000 for leading-edge ingenuity in MEMS and mixed-signal designs

SAN JOSE, Calif., November 2, 2016Cadence Design Systems, Inc. (NASDAQ: CDNS), Coventor, X-FAB and Reutlingen University have teamed up to launch the MEMS design contest to encourage the development of innovative MEMS and mixed-signal designs. The first-prize winner will receive a $5000 cash award, have their design manufactured at X-FAB’s wafer production facilities and get a free one-year license of Coventor’s MEMS design software. The second and third prize winners will receive $2,000 and $1,000 cash prizes respectively, along with a private tour of X-FAB’s foundry facilities. The contest registration is open until December 31, 2016, and design teams are encouraged to enter the contest at http://info.coventor.com/mems-design-contest-2018. read more…

Achieving the Vision of Silicon Photonics Processing

By: Sandy Wen, MSEE, Semiconductor Process and Integration Engineer, Coventor

Silicon Photonics Test Die

Silicon Photonics Test Die

With the increasing need for faster data transfer rates, the transition from electrical to optical signaling in data processing is inevitable.   Copper cabling cannot keep up with the upcoming data center bandwidth requirements, for applications such as multimedia streaming and high performance computing.  One technology that could enable true optical communication is silicon photonics. read more…

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Design Process Technology Co-Optimization for Manufacturability

By:   Dalong Zhao – Semiconductor Process & Integration Engineering

Yield and cost have always been critical factors for both manufacturers and designers of semiconductor products.   Meeting yield and product cost targets is a continuous challenge, due to new device structures and increasingly complex process innovations introduced to achieve improved product performance at each new technology node.  Design for manufacturability (DFM) and design process technology co-optimization (DTCO) are widely used techniques that can ensure the successful delivery of both new processes and products in semiconductor manufacturing.   In this article, we will discuss how 3D (3 dimensional) DTCO can be used to improve product yield and accelerate product delivery dates in semiconductor manufacturing. read more…

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When Galaxies Collide – Synopsys TCAD and Coventor Start to Overlap

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By Bryon Moyer

Astronomy bestows lavish breathless anticipation upon one of the great events of the universe: two galaxies running into (or through) each other. The thing is, it happens breathtakingly slowly – each stately galaxy spinning away, the distance between them slowly evaporating. Watching it is something of a sampling exercise: see where they are; nap for a couple of centuries. Wake, see that, yup, they’re a little closer; nap. Wake again, grab a new beer, and doggonnit if they aren’t just a wee bit closer yet. Basketball it’s not.

Well, we may have something of a similar event in play in EDA-land. Although referring simply to two galaxies isn’t quite fair: one, Synopsys, is perhaps more of a galaxy cluster to Coventor’s galaxy. To set the scene, let’s examine the status quo – the gap between the companies – and then we’ll look at each one to see how that gap is closing. And we’ll hopefully do it in a way that doesn’t involve napping.

read the full article here.