Registration for Worldwide MEMS Design Contest Opens
Cadence, X-FAB, Coventor and Reutlingen University offering a first prize of $5000 for leading-edge ingenuity in MEMS and mixed-signal designs
SAN JOSE, Calif., November 2, 2016—Cadence Design Systems, Inc. (NASDAQ: CDNS), Coventor, X-FAB and Reutlingen University have teamed up to launch the MEMS design contest to encourage the development of innovative MEMS and mixed-signal designs. The first-prize winner will receive a $5000 cash award, have their design manufactured at X-FAB’s wafer production facilities and get a free one-year license of Coventor’s MEMS design software. The second and third prize winners will receive $2,000 and $1,000 cash prizes respectively, along with a private tour of X-FAB’s foundry facilities. The contest registration is open until December 31, 2016, and design teams are encouraged to enter the contest at http://info.coventor.com/mems-design-contest-2018. read more…
By: Sandy Wen, MSEE, Semiconductor Process and Integration Engineer, Coventor
Silicon Photonics Test Die
With the increasing need for faster data transfer rates, the transition from electrical to optical signaling in data processing is inevitable. Copper cabling cannot keep up with the upcoming data center bandwidth requirements, for applications such as multimedia streaming and high performance computing. One technology that could enable true optical communication is silicon photonics. read more…
By: Dalong Zhao – Semiconductor Process & Integration Engineering
Yield and cost have always been critical factors for both manufacturers and designers of semiconductor products. Meeting yield and product cost targets is a continuous challenge, due to new device structures and increasingly complex process innovations introduced to achieve improved product performance at each new technology node. Design for manufacturability (DFM) and design process technology co-optimization (DTCO) are widely used techniques that can ensure the successful delivery of both new processes and products in semiconductor manufacturing. In this article, we will discuss how 3D (3 dimensional) DTCO can be used to improve product yield and accelerate product delivery dates in semiconductor manufacturing. read more…
Tagged Coventor, Design Rule Checks, Design Technology Co-Optimization, DRC, DTCO, hotspot, lithography, multi-patterning, Process Development, Process Modeling, Process Simulation, semiconductor process modeling, semiconductor process variation, SEMulator3D
By Bryon Moyer
Astronomy bestows lavish breathless anticipation upon one of the great events of the universe: two galaxies running into (or through) each other. The thing is, it happens breathtakingly slowly – each stately galaxy spinning away, the distance between them slowly evaporating. Watching it is something of a sampling exercise: see where they are; nap for a couple of centuries. Wake, see that, yup, they’re a little closer; nap. Wake again, grab a new beer, and doggonnit if they aren’t just a wee bit closer yet. Basketball it’s not.
Well, we may have something of a similar event in play in EDA-land. Although referring simply to two galaxies isn’t quite fair: one, Synopsys, is perhaps more of a galaxy cluster to Coventor’s galaxy. To set the scene, let’s examine the status quo – the gap between the companies – and then we’ll look at each one to see how that gap is closing. And we’ll hopefully do it in a way that doesn’t involve napping.
read the full article here.
By PD&D Staff, Product Design and Development
In the Product Design & Development Brainstorm, we talk with industry leaders to get their perspective on issues critical to the design engineering marketplace.
In this issue, we ask: What are some of the key technology trends that will shape the evolution of the wearables market?
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A*STAR IME’S CONSORTIUM TO DEEPEN CAPABILITIES IN MEMS TECHNOLOGIES FOR INDUSTRIAL INTERNET OF THINGS, AUTOMOTIVE, AND INDOOR NAVIGATION APPLICATIONS
A*STAR IME’s collaborative partnership with industry will enable the development of cutting-edge industrial-grade sensors to heighten performance and achieve cost-effectiveness for MEMS devices
IMEC Partner Technical Week Review
By: Aurélie Juncker, Semiconductor Process & Integration Engineer
a. Fully aligned Via with Cu recess approach – Gayle Murdoch, b. STT-RAM – Davide Crotti, c. N10 Supernova2 process – Matt Gallagher
In March 2016, Coventor was invited to the biannual Partner Technical Week (PTW) at IMEC in Leuven, Belgium. IMEC, a world-leading research group in nanotechnology, organizes their Partner Technical Week every 6 months to present scientific results to their partners. During this week, a number of specialists from IMEC’s many partner companies also discuss their progress in areas related to IMEC’s research. This event brings together a large number of engineers who are specialists in their domain, and provides an interesting forum to leverage the scientific knowledge gained by IMEC and its partners. read more…
Tagged 7 nm, BEOL, Coventor, DOE, DUV, ETCH, EUV, FEOL, i193, lithography, misalignment, multi-patterning, N7, patterning, virtual fabrication
By Luke Collins, Tech Design Forum
Coventor has updated its SEMulator3D virtual fabrication tool so it can extract predicted resistance and capacitance values from its models. The analysis tool could be used to speed up the availability of early PDKs for rapidly evolving processes.
SEMulator3D abstracts IC manufacturing steps into behavioural models, so that it can simulate a a whole process in a ‘virtual fab’. Because the process steps are modeled using behavioural abstractions, rather than full physics, it becomes practical to run multiple options to explore how variations in each step will affect overall outcomes.
read the full article here