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Coventor Announces SEMulator3D 6.0 and New Electrical Analysis Capabilities

Coventor’s Virtual Fabrication Platform Addresses Increasingly Complex Semiconductor Process Design Challenges

CARY, NC– June 6, 2016 – Coventor®, Inc., the leading supplier of automated software solutions for semiconductor devices and micro-electromechanical systems (MEMS), today announced the availability of SEMulator3D® 6.0 – the latest version of its semiconductor virtual fabrication platform. This new version further increases the accuracy of the process simulation, geometry and modeling of advanced semiconductor processes with new features, usability enhancements and a new add-on capability for electrical analysis. Along with SEMulator3D 6.0, Coventor is releasing an all-new SEMulator3D Electrical Analysis add-on component that allows seamless resistance and capacitance extraction directly from SEMulator3D process-predictive 3D models. read more…

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Will directed self-assembly pattern 14nm DRAM?

By: Mattan Kamon, PhD., Distinguished Technologist, R&D, Coventor

Matt's March 2016 Blog Graphic

But first, more generally, will directed self-assembly (DSA) join Extreme Ultraviolet (EUV) Lithography and next generation multi-patterning techniques to pattern the next memory and logic technologies?  Appealing to the wisdom of crowds, the organizers of the 2015 1st International DSA symposium recently surveyed the attendees, and nearly 75% believed DSA would insert into high volume manufacturing within the next 5 years, and nearly 30% predicted insertion within the next 2 years.   What is gating insertion?  The crowd rated defectivity as the most critical issue facing DSA.  This fact adds weight to memory being the first to be patterned with DSA.  This is because, as Roel Gronheid from IMEC pointed out last month at the SPIE Advanced Lithography conference [1], memory chips can tolerate single failing cells through redundancy and so can could tolerate higher defectivity in patterning (roughly 1 defect/cm2 compared to 0.01 defect/cm2 for logic).  Defectivity rates for DSA aren’t there yet (according to public information), but are rapidly approaching [2], [3]. read more…

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New MEMS Design Contest Encourages Advances in MEMS Technology

MEMS Design contest company header image

Industry leaders in EDA & foundry services collaborate with academia to explore future possibilities of CMOS/MEMS integration  

Dresden, Germany – March 16, 2016 – Jointly sponsored by Cadence Design Systems, Coventor, X-FAB and Reutlingen University, a new MEMS Design Contest is being launched at DATE 2016.  The objective of this contest is to encourage greater ingenuity with regard to the integration of MEMS devices and mixed-signal CMOS blocks.  To kick off the contest, an informative session will be held in the Exhibition Theatre on Thursday, March 17, 2016 from 14:00 to 17:30 and is open to all DATE attendees free of charge. read more…

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The Sensor Swarm Arrives

By Tom Kevan, Desktop Engineering

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It all started with smartphones and airbags. Design engineers began to integrate sensors in growing numbers into such systems to enable smarter performance. These applications mark the prelude to what Alberto Sangiovanni-Vincentelli, a professor at University of California, Berkeley, describes as a “sensory swarm” — a flood of heterogeneous sensors interfacing the cyber and physical worlds. By 2025, experts predict that the swarm could number as many as 7 trillion devices.

One of the first stages in the realization of this sensor-dominated world, the Internet of Things (IoT) requires technologies that can take on smaller form factors and operate on miserly power budgets. In their search to find sensing devices that can meet these requirements, designers have turned to micro-electromechanical systems, or MEMS. Before they can take full advantage of the miniaturization the technology offers and expand its role in the marketplace, engineers must be able to bridge the gaps between the MEMS, analog and digital design worlds. To do this, they will require a new set of tools.

read the full article here

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Directed self assembly may offer similar benefits to EUV, process modeling study says

By Luke Collins, Tech Design Forum

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Directed self assembly (DSA) techniques may offer similar advantages in terms of process variation control as EUV lithography, according to a study carried out using 3D behavioral process modeling techniques.

This could reduce fab cycle times, ease process integration and save costs in advanced semiconductor processes, especially for DRAMs, whose regular structures are well-suited to the use of DSA.

read the full article here

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Webinar: Leveraging MEMS prototyping platforms for research and commercialization – February 23, 2016

CMCLogo_HighResLeveraging MEMS prototyping platforms for research and commercialization

Coventor is pleased to announce a webinar offered by CMC Microsystems, a provider of Coventor’s MEMS Design solutions.

CMC Microsystems, recognized worldwide for research excellence and for advancing innovations in micro and nano technologies, is pleased to offer a free webinar on MEMS research and commercialization.   The webinar,  entitled “Leveraging MEMS prototyping platforms for research and commercialization”, will be offered on Tuesday, Feb. 23, 2016 at 9:00 a.m. EST and at 2:00 p.m. EST.

REGISTER NOW:  http://www.cmc.ca/en/NewsAndEvents/Webinars/MEMSWebinar.aspx)  to learn how MEMS multi-project wafer services can help you bring your MEMS product to market

The speakers will review the development of a wide array of MEMS devices using the MEMS Integrated Design for Inertial Sensors (MIDIS) fabrication process introduced by Teledyne DALSA Semiconductor Inc., along with a discussion regarding micro-electrostatic actuators fabricated using the Micralyne MicraGEM-Si™ MEMS Fabrication Process.

Please join CMC Microsystems to learn how two leading Canadian organizations have leveraged MEMS multi-project wafer services to move their novel concepts towards commercial readiness.

Webinar Details

Sponsor:  CMC Microsystems

Event:   Webinar – “Leveraging MEMS prototyping platforms for research and commercialization”

Date:  Tuesday, Feb. 23, 2016 at 9:00 a.m. EST and 2:00 p.m. EST

REGISTER FOR WEBINAR AT: http://www.cmc.ca/en/NewsAndEvents/Webinars/MEMSWebinar.aspx

 

 

 

 

Advanced Lithography and Process Variation Modeling Using SEMulator3D

LER_Animation

Click on image to view animation of modeling

By:   Jimmy Gu, Coventor Technical Staff

One of the top and probably toughest challenges that process integrators are facing today in a silicon fab is process variability. As a former process integrator working hard to ramp up the yield of 22nm FinFET technology, I saw it first-hand. Looking back, I wish I was equipped with the SEMulator3D virtual fabrication platform, which is designed to address this type of process variability challenge. With the recent release of SEMulator3D 5.1, its process variability toolbox has just received a powerful new addition: the ability to model line edge roughness (LER) and line width roughness (LWR) in lithography. read more…

Coventor ASML IMEC: The last half nanometer

By Scotten Jones, SemiWiki
Short SemiWiki logo
On Tuesday evening December 8th at IEDM, Coventor held a panel discussion entitled the “The Last Half Nanometer”. Coventor is a leading provider of simulation software used to design processes. This is my third year attending the Coventor panel discussion at IEDM and they are always excellent with very strong panels and discussion. The panel was made up of David Fried CTO of Coventor, Alek Chen from ASML, Aaron Theon of IMEC, and Subramanian Iyer from UCLA. Subramanian acted as both a panelist and the moderator.

read the full article here

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