Author Archives: Michael Hargrove

Linking Virtual Wafer Fabrication Modeling with Device-level TCAD Simulation

By Mike Hargrove

Most process/device simulation tools are TCAD-based. By this, I mean they share a common platform which connects the process simulator to the device simulator, usually using the same mesh structure. Most all of these TCAD tools are finite-element based, and the 3D final mesh structure is tetrahedral in nature. The mesh structure contains many nodes which define solution points for the numerous complex set of equations required to create the physical structure, in most cases a transistor, and solve for the electrical characteristics of the device. One of the drawbacks of TCAD is the computational time required to arrive at a solution – both process model solution and device electrical solution. A larger modeled area (e.g. multiple transistors and/or an SRAM cell) usually means longer simulation time.

Coventor’s virtual wafer fabrication approach addresses this challenge. Our process modeling platform combines with the statistical device TCAD suite of tools from Gold Standard Simulations, LTD. (GSS) to produce SRAM device-level simulation capability capturing real process-induced statistical variation. The ultimate objective of statistical device modeling is to capture the intrinsic variation of physically relevant process parameters. The combination of Coventor SEMulator3D process modeling capability and GSS statistical TCAD simulator GARAND fulfills this objective.
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Some Thoughts on 3D Integration and How to Better Understand its Complexity

As semiconductor technology scales into the 20nm node and beyond, the process complexity, electrical performance and circuit density tradeoff becomes extremely difficult to optimize. As the demand for increased density, lower power, and higher bandwidth accelerates, the motivation for 3D integration becomes more attractive. With the advent of 3D integration comes the promise of “beyond Moore’s law” integration by stacking chip-on-chip and connecting them with through-silicon-vias (TSVs). Numerous definitions of 3D integration exist, for example multi-die packages (also known as system-in-package, or SiP) in which multiple die are mounted on a common substrate that connects them, package-in-package (PiP) where a number of SiPs are mounted in a larger SiP, and package-on-package (PoP) where one SiP is mounted on top of another SiP. All of these approaches offer some degree of density advantage, however, the ultimate objective of 3D integration is the multiple stacking of silicon levels on top of one another, each of which contain subsequent levels of circuitry, all connected with TSVs. This approach to 3D integration has been demonstrated by CEA-Leti and reported in IEEE Spectrum (see Figure 1 below). read more…