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SEMulator3D Honored as UBM ACE Award Finalist
Coventor’s Virtual Fabrication Platform Recognized for Significantly Improving Electronics Manufacturing
CARY, NC– November 17, 2017 – Coventor®, Inc. a Lam Research Company and leading supplier of virtual fabrication solutions for semiconductor and micro-electromechanical systems (MEMS) devices, today announced its 3D virtual fabrication platform, SEMulator3D®, has been named a finalist in UBM’s annual ACE Awards competition.
The ACE (Annual Creativity in Electronics) Awards, in partnership with EE Times and EDN, showcase the best of the best in today’s electronics industry, including the hottest new products, start-up companies, design teams, executives, and more. ACE finalists and winners are hand selected by a panel of EE Times and EDN editors as well as independent judges from the across the industry. read more…
By: Michael Hargrove, SP&I Engineer
Reducing back-end-of-line (BEOL) interconnect parasitic capacitance remains a focus for advanced technology node development. Porous low-k dielectric materials have been used to achieve reduced capacitance, however, these materials remain fragile and prone to reliability concerns. More recently, air gap has been successfully incorporated into 14nm technology , and numerous schemes have been proposed to create the air gap [2-3]. There are many challenges to integrate air gap in BEOL such as process margin for un-landed vias and overall increased process complexity. In this paper, we introduce virtual fabrication (SEMulator3D®) as a means to study air gap process integration optimization and resulting interconnect capacitance reduction. Initial calibration to published air gap data is demonstrated. read more…
By: Jimmy Gu, SP&I Staff Engineer
Trial and error wafer fabrication is commonly used to study the effect of process changes in the development of FinFET and other advanced semiconductor technologies. Due to the interaction of upstream unit process parameters (such as deposition conformality, etch anisotropy, selectivity) during actual fabrication, variations based upon process changes can be highly complex. Process simulators that mimic fab unit processes can now be used to model these complex interactions. They can also help process engineers identify important process and/or design parameters that drive certain critical targets such as CDs, yield limiting spacing, 3D design rule violations, resistance/capacitance, and other process and design issues. The number of possible parameters that affect device performance and yield can be quite large, so statistical analysis can provide useful insight and help identify critical performance parameters. Coventor’s SEMulator3D virtual fabrication (or process simulation) platform contains an analytics module for conducting virtual design-of-experiments and statistical analysis. I would like to use an example of a 14nm FinFET process flow in SEMulator3D to identify important process parameters that drive fin top CD, which is a key metric for transistor performance.
Lam Research completes acquisition of Coventor
EuroTrade – September 6, 2017
Lam Research, a supplier of wafer fabrication equipment and services to the semiconductor industry, has completed the acquisition of Coventor, a provider of simulation and modeling solutions for semiconductor process technology, micro-electromechanical systems (MEMS), and the Internet of Things (IoT).
Lam said the acquisition supports its advanced process control vision and is expected to accelerate process integration simulation to increase the value of virtual processing, further enabling chipmakers to address some of their most significant technical challenges. read more…