Author Archives: Sandra Liu

Technical Tidbits from IWLPC and MSEC 2017

By Francoise von Trapp

It’s been a busy few weeks for me as I attended both the International Wafer Level Packaging Conference (IWLPC), October 24-26, 2017 at the DoubleTree in San Jose and SEMI-MSIG’s MEMS and Sensors Executive Congress, October 31-Nov. 2, at the Hayes Mansion in San Jose. In addition to taking in some great keynotes and technical sessions, I had the opportunity to meet with several companies to find out what’s new.

read the full article here.

Lam’s Coventor Buy Boosts MEMS Manufacturing

By R. Colin Johnson

SAN JOSE, Calif.—Why did Lam Research, a semiconductor fab equipment supplier, acquire Coventor, a software house hawking software to design microelectromechanical system (MEMS) chips and sub-10 nanometer semiconductors such as 3D finFETs?

Analysts fully expected for Coventor to be absorbed by Lam Research, only to surface as a Lam software offering. But at SEMI’s MEMS & Sensor Executive Congress 2017 (MSEC) here the companies reported that they are staying in separate headquarters, depending more the synergy of co-designing hardware for software and visa versa to give them a competitive edge over the competition.

read the full article here.

MEMS Market Shifting

By Ed Sperling

The MEMS sector is beginning to look more promising, bolstered by new end-market demand and different packaging options that require more advanced engineering, processes and new materials. All of this points to higher selling prices, which are long overdue in this space.

For years, the market for microelectromechanical systems was populated by too many companies vying for too few opportunities. Some devices became commoditized to the point where costs failed to keep up with selling price reductions. Even in the more specialized and higher-margin fringes of this segment, such as MEMS-based microphones and speakers, market sizes were too small to support more than a handful of smaller companies.

read the full article here.

Reducing BEOL Parasitic Capacitance using Air Gaps

By: Michael Hargrove, SP&I Engineer

Reducing back-end-of-line (BEOL) interconnect parasitic capacitance remains a focus for advanced technology node development. Porous low-k dielectric materials have been used to achieve reduced capacitance, however, these materials remain fragile and prone to reliability concerns. More recently, air gap has been successfully incorporated into 14nm technology [1], and numerous schemes have been proposed to create the air gap [2-3].  There are many challenges to integrate air gap in BEOL such as process margin for un-landed vias and overall increased process complexity. In this paper, we introduce virtual fabrication (SEMulator3D®) as a means to study air gap process integration optimization and resulting interconnect capacitance reduction. Initial calibration to published air gap data is demonstrated. read more…

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Using Advanced Statistical Analysis to improve FinFET transistor performance

By: Jimmy Gu, SP&I Staff Engineer

Trial and error wafer fabrication is commonly used to study the effect of process changes in the development of FinFET and other advanced semiconductor technologies.  Due to the interaction of upstream unit process parameters (such as deposition conformality, etch anisotropy, selectivity) during actual fabrication, variations based upon process changes can be highly complex. Process simulators that mimic fab unit processes can now be used to model these complex interactions.  They can also help process engineers identify important process and/or design parameters that drive certain critical targets such as CDs, yield limiting spacing, 3D design rule violations, resistance/capacitance, and other process and design issues.   The number of possible parameters that affect device performance and yield can be quite large, so statistical analysis can provide useful insight and help identify critical performance parameters.  Coventor’s SEMulator3D virtual fabrication (or process simulation) platform contains an analytics module for conducting virtual design-of-experiments and statistical analysis. I would like to use an example of a 14nm FinFET process flow in SEMulator3D to identify important process parameters that drive fin top CD, which is a key metric for transistor performance.

read more…

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Lam Research Acquires Simulation and Modeling Solutions Firm Coventor

Lam Research completes acquisition of Coventor

EuroTrade – September 6, 2017

Lam Research, a supplier of wafer fabrication equipment and services to the semiconductor industry, has completed the acquisition of Coventor, a provider of simulation and modeling solutions for semiconductor process technology, micro-electromechanical systems (MEMS), and the Internet of Things (IoT).

Lam said the acquisition supports its advanced process control vision and is expected to accelerate process integration simulation to increase the value of virtual processing, further enabling chipmakers to address some of their most significant technical challenges. read more…

Why Fabs Worry About Tool Parts

By Mark Lapedus

Achieving high yields with acceptable costs is becoming much more difficult as chipmakers migrate to next-generation 3D NAND and finFET devices—but not just because of rising complexity or lithography issues.

To fabricate an advanced logic chip, for example, a wafer moves from one piece of equipment to another in what amounts to 1,000 process steps or more in a fab. Any glitch with the equipment or a process step can cause defects, thereby impacting yield. The culprit may be a malfunction in seemingly insignificant parts or sub-systems in the equipment itself.

read the full article here.

Senior C++ Computational Physics/Math Developer for Semiconductor Applications – Waltham, MA

Senior C++ Computational Physics/Math Developer for Semiconductor Applications – Waltham, MA

At Coventor, a Lam Research company, we build innovative software products to solve semiconductor technology challenges.  Our 3D modeling software is revolutionizing the way that semiconductor chips are fabricated around the world.  Enabled by our core intellectual property – an accelerated 3D voxel modeling and visualization engine – our software is evolving fast as our business and customer base expands rapidly.

Coventor’s modeling team builds the core capabilities of SEMulator3D; the ability to model a wide variety of physical phenomena accurately and efficiently using a variety of numerical techniques.  As a key member of our modeling team you will implement new algorithms for modeling a wide range of semiconductor processes and phenomena such as plasma etching, chemical-mechanical polishing, and electrical behavior.  This is a hands-on software development position, requiring proficiency in C++ and expertise in and physical modeling. Your title, level of responsibility, creative freedom and salary will be commensurate with your education and experience.

Great engineering is Coventor’s heart and soul.  Our software is envisioned and created by world-class engineers in many disciplines: software engineering, numerical physics, statistics, electrical engineering, quality assurance and development operations.  Since our inception as an MIT spin-off, we’ve focused on agility by enabling individuals to take initiative and find innovative solutions to hard problems.  With our recent acquisition by Lam Research we have access to many more resources, and exciting opportunities for collaboration within the company. We are looking to hire engineers with broad skills who are ready to contribute in multiple ways, to enable our customers’ success.

Responsibilities:

  • Research, prototype and characterize methods for simulation of physical phenomena associated with fabrication and/or behavior of nanoscale semiconductor devices
  • Implement new modeling algorithms in C++, using and extending existing modeling infrastructure and APIs
  • Optimize algorithms for speed, including profiling and parallel implementation
  • Participate in general software engineering tasks, including verification, testing, bug fixing and maintenance of existing code

 

Required Qualifications (all of the following):

  • PhD in Engineering or Physical Science discipline, or Computer Science with a numerical simulation focus.
  • Direct experience implementing modeling/simulation algorithms in three dimensions, using methods such as finite-difference, finite-element, particle, atomistic, cellular automata etc.
  • Strong  C++ coding skills, including use of the standard template library
  • Strong math skills, including a thorough knowledge of calculus
  • Desire to collaborate, contribute to, and learn from a team

 

Desirable Qualifications (any of the following):

  • General knowledge of semiconductor processing technology
  • Direct experience with implementation of software solutions for non-linear partial differential equations
  • Experience solving systems outside of the semiconductor space such as convection-diffusion or stress/strain
  • Experience in modeling or fabrication of nanoscale semiconductor devices
  • Experience with cross-platform development, on Windows and Linux
  • Experience with one or more of: Boost, C++11 or later, Python
  • Experience programming GPUs for simulation (GPGPU using Cuda or the like).

 

This regular, full-time position is located in Waltham, MA. Coventor offers comprehensive benefits and is an EEO/AA Employer. You must be a current legal resident of the U.S. or have a valid U.S. visa to apply for this position.  Please e-mail your cover letter and resume to job1864@coventor.com.