Author Archives: Sandra Liu

The Race To 10/7nm

By Mark Lapedus

Amid the ongoing ramp of 16/14nm processes in the market, the industry is now gearing up for the next nodes. In fact, GlobalFoundries, Intel, Samsung and TSMC are racing each other to ship 10nm and/or 7nm technologies.

The current iterations of 10nm and 7nm technologies are scaled versions of today’s 16nm/14nm finFETs with traditional copper interconnects, high-k/metal-gate and low-k dielectrics. In finFETs, the control of the current is accomplished by implementing a gate on each of the three sides of a fin.

read the full article here.

What drives SADP BEOL variability?

By: Michael Hargrove, Semiconductor Process & Integration Engineer

Until EUV lithography becomes a reality, multiple patterning technologies such as triple litho-etch (LELELE), self-aligned double patterning (SADP), and self-aligned quadruple patterning (SAQP) are being used to meet the stringent patterning demands of advanced back-end-of-line (BEOL) technologies.  For the 7nm technology node, patterning requirements include a metal pitch of 40nm or less. This narrow pitch requirement forces the use of spacer based pitch multiplication techniques. Unfortunately, these techniques have high process/lithography variability, which can severely impact RC and overall device performance.

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Coventor Touts Unified MEMS Platform

By R. Colin Johnson

LAKE WALES, Fla. — Micro-electro-mechanical systems (MEMS) chips cannot be virtually fabricated using conventional electronic design automation (EDA) tools because their three-dimensional structures cannot be represented well there. Computer Aided Design (CAD) tools are closer to the mark, but usually work on millimeter- instead of micron-size scales.

To bridge the gap, Coventor Inc. (Cary, North Carolina) has created its Coventor and MEMS+ tools, which have now been merged into a single unified platform perfect for Internet of Things (IoT) makers, according to Steve Breit, vice president of MEMS business for Coventor.

read the full article here.

Reworking Established Nodes

By Ed Sperling

New technology markets and a flattening in smartphone growth has sparked a resurgence in older technology processes. For many of these up-and-coming applications, there is no compelling reason to migrate to the latest process node, and equipment companies and fabs are rushing to fill the void.

As with all electronic devices, the focus is on cost-cutting. But because these markets are likely to generate lower volumes than mobile phones or PCs, the majority of those savings will not come from shrinking features. In many cases, these are either original designs (rather than derivatives), and the technologies are still being developed. Some are custom, some are partially custom, and most are heterogeneous. Designing and manufacturing them using finFET processes would be price-prohibitive.

read the full article here.

The Week In Review: IoT

By Jeff Dorsch

Coventor this week introduced its CoventorMP 1.0 platform, meant to provide a simpler, unified environment for designing microelectromechanical system devices in IoT applications. The platform brings together the company’s CoventorWare and MEMS+ design software tools. With the platform, MEMS sensors and actuators can be integrated into system-in-package components for IoT devices.

read the full article here.

Coventor Launches CoventorMP 1.0, a New Unified Environment for Designing MEMS for IoT Devices

Coventor’s advanced design platform provides seamless MEMS/IoT design and integration

CARY, NC– May 10, 2017 – Coventor®, Inc., the global market leader in design automation solutions for microelectromechanical systems (MEMS) and virtual fabrication of MEMS and semiconductor devices, today announced the immediate availability of CoventorMP® 1.0, a new unified MEMS design platform. CoventorMP 1.0 combines the complementary strengths of Coventor’s industry-leading software tools for MEMS design, CoventorWare® and MEMS+®, into a single powerful environment for MEMS design automation. The new platform provides a cohesive environment where designs can be entered once and used to create conventional finite element models (CoventorWare) and compact finite element models (MEMS+). CoventorMP 1.0, which includes enhanced versions of CoventorWare (Version 10.2) and MEMS+ (Version 6.2), provides a seamless path for integrating MEMS sensors and actuators into System-in-Package (SiP) components targeted at Internet of Things (IoT) devices. read more…

Inside Next-Gen Transistors

By Mark LaPedus

Coventor’s CTO looks at new types of transistors, the expanding number of challenges at future process nodes, and the state of semiconductor development in China.

David Fried, chief technology officer at Coventor, sat down with Semiconductor Engineering to discuss the IC industry, China, scaling, transistors and process technology. What follows are excerpts of that conversation.

read the full article here.

Photoresist shape in 3D: Understanding how small variations in photoresist shape significantly impact multi-patterning yield

By: Mustafa B. Akbulut, Ph.D., Team Lead, Quality Assurance, Semiconductor Solutions

Things were easy for integrators when the pattern they had on the mask ended up being the pattern they wanted on the chip. Multi-patterning schemes such as Self-Aligned Double Patterning (SADP) and Self-Aligned Quadruple Patterning (SAQP) have changed that dramatically. Now, what you have on the mask determines only a part of what you will get at the end. read more…

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