Challenges in 3D NAND Flash Processing

With 2D planar NAND flash hitting scaling issues at sub-20nm technology nodes, 3D NAND flash has become all the rage. Instead of restricting memory cells to a single plane and scaling the devices horizontally, memory cells can also be stacked vertically, allowing high cell density while side-stepping scaling issues (for now). Major NAND flash manufacturers have each developed their own designs and technology for 3D NAND flash, and with the addition of vertical cell stacking, new issues in 3D process integration arise.

For instance, in Samsung’s Terabit Cell Array Transistor (TCAT) technology [1], a memory cell array is formed of NAND flash strings with vertically-oriented channels and word lines arranged in planes. Of particular interest is the gate integration scheme: TCAT uses charge-trapping (SONOS/TANOS) with metal replacement gates, the combination which is expected to result in faster erase speed, wider threshold voltage margins, etc. The cell gates are created using a sacrificial nitride layer combined with a damascene process: the entire stack of SiO2/SiN layers is etched (“word line cut”) after staircase formation, then nitride is removed through wet etching with hot phosphoric acid, leaving behind gaps separated by the oxide. These gaps are then filled with dielectric and gate metal to create gate-all-around structures.

Figure 1. 3D NAND flash memory array, based on TCAT [1], with 16 cells per string, top gate-select layer and bottom source-select layer.

Figure 1. 3D NAND flash memory array, based on TCAT [1], with 16 cells per string, top gate-select layer and bottom source-select layer.

TCAT replacement gate processing was investigated using SEMulator3D, with the process integration based on publicly available sources [1-2]. In the first attempt at a 3D model (Figure 2a), the sacrificial SiN removal resulted in unsupported SiO2 beams, not unlike cantilever structures that result from release etching in MEMS processing — but not commonly found in memory or logic devices. This initial model looked untenable and did not make much sense, particularly if more cells (24-32 total) are to be added.

After stumbling on some Samsung patents [3] and evaluating other process flows, the model was revised to include a capping dielectric (oxide) to cover the staircase during word line cut and before SiN removal (Figure 2b). While the cap holds the oxide layers together and avoids free-standing oxide beams, the word line cut required some adjustment: both the oxide/nitride stack and the capping dielectric should be etched fully, so that an optimal etch process requires control of the etch selectivity of oxide to nitride, and vice versa.

Figure 2. (a) First iteration of the TCAT model after sacrificial SiN removal results in unsupported oxide beams. (b) Second iteration of the model now has top dielectric to hold the oxide layers together during SiN removal.

Figure 2. (a) First iteration of the TCAT model after sacrificial SiN removal results in unsupported oxide beams. (b) Second iteration of the model now has top dielectric to hold the oxide layers together during SiN removal.

Gate stack processing is but one of the many process integration issues in 3D NAND flash processing. Other challenges with vertically-stacked memory cells include film deposition uniformity and high-aspect ratio etching. And with flash memory design being taken to its extremes, it is an exciting time to be a memory process integrator!

References
[1] J. Jang et al, “Vertical cell array using TCAT(Terabit Cell Array Transistor) technology for ultra high density NAND flash memory,” VLSIT 2009.
[2] W. Cho et al, “Highly reliable vertical NAND technology with biconcave shaped storage layer and leakage controllable offset structure,” VLSIT 2010.
[3] B. Jang et al, “Methods of manufacturing three dimensional semiconductor memory devices using sub-plates” US Patent 8,697,498,.

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