Future Outlook: The Advantages of Fully Depleted Silicon on Insulator (FD-SOI) Technology

By: Michael Hargrove, SP&I Engineer

If my memory serves me well, it was at the 1989 Device Research Conference where the potential merits of SOI (Silicon on Insulator) technology were discussed in a heated evening panel discussion. At that panel discussion, there were many advocates for SOI, as well as many naysayers. I didn’t really think more about SOI technology until the mid-nineties, when I was sitting in a meeting where the first SOI device data was being presented in the hallowed halls of IBM. The data was incredibly scattered and my thinking was “this technology is going nowhere!” The purported performance advantage was stated to be ~35%, simply due to the capacitance reduction (no longer did the bottom junction capacitance play a role) and the speed advantages of stacked devices in a NAND circuit. It all sounded great, but in the mid-nineties, the data simply didn’t support it. Nonetheless, the SOI advocates pursued their beloved technology, and the rest is history. SOI technology has been part of IBM’s main stream high-performance technology base through the 14nm node, including FinFETs on SOI.

While IBM pursued SOI, every other semiconductor manufacturer stayed with bulk silicon technology.  As we all know, bulk silicon technology is now the dominant technology in the high-performance CPU/GPU arena. However, as transistor scaling has continued through the last decade, the tradeoff between power and performance has become very important in today’s world of handheld electronics. Controlling off-state leakage current, while maximizing transistor switching speeds, is the name of the game. Within these constraints, the merits of SOI technology are being demonstrated in the extremely scaled SOI known as fully-depleted SOI, or FD-SOI. STMicroelectronics was the first major semiconductor company to demonstrate FD-SOI as a possible contender to capture the low-power/high-performance market. GlobalFoundries has followed this path as well, having introduced FD-SOI technology at the 22nm node, and is working on 12nm FD-SOI.

There are many reasons for this interest in FD-SOI. It is a planar technology, so the process complexity is reduced compared to 3D technology. It also delivers the benefits of reduced silicon geometries, namely, power and performance, and provides additional functionality by enabling substrate bias. The basic FD-SOI structure is shown in Figure 1. As noted, it is a planar technology with a very thin silicon layer (channel) on top of a buried oxide. The very thin silicon channel layer, which is fully depleted (free of intrinsic charge carriers), improves the gate’s ability to control the channel and ultimately turn it off when the transistor is off. The buried oxide helps isolate the source and drain regions, which improves drain-induced barrier lowering (DIBL) and enables lower operating voltage to reduce power consumption.

FD-SOI, Fully Depleted SOI, SOI, Silicon on Insulator

Fig. 1. Basic cross-section of an FD-SOI transistor. (Source: STMicroelectronics)

FD-SOI, Silicon on Insulator, SOI, Fully Depleted Silicon on Insulator

Fig. 2. FD-SOI transistor with substrate contact for biasing. (Source: STMicroelectronics)

 

 

 

 

 

One other “degree of freedom” attributed to FD-SOI is the ability to bias the substrate (see Fig. 2). This allows both forward and reverse bias, enabling designers to dynamically raise or lower the threshold voltage and optimize power and performance.

Another attribute of FD-SOI is its ability to mitigate “history effect”, which is the tendency for electrical charge to remain in the SOI body after the transistor is turned off. The nature of a fully-depleted body does away with this issue, which designers had to previously account for in standard SOI. Multi-Vt (threshold voltage) devices are a bit more difficult to achieve with FD-SOI since there is no channel doping, typically used to alter Vt in bulk technologies. The substrate bias is an obvious way to get around this design issue, while at the same time improving random doping fluctuations due to the lack of channel doping.

Overall, FD-SOI technology offers many advantages over standard bulk-Si technologies. The main advantage is the power/performance tradeoff due to its improved electrostatics. It also offers SRAM designers the ability to operate at lower voltages, has reduced variability due to random doping fluctuations, and provides impeccable SER (soft error rate) protection. FD-SOI also offers benefits for RF and analog designs due to its total dielectric isolation, which eliminates any threat of latch-up, along with an absence of channel and pocket doping, which lowers noise coupling and improves gain.

SOI and FD-SOI technologies have achieved commercial success since the 1990’s, due to their inherent advantages in low-power, high-performance applications.  FD-SOI has many advantages compared to bulk silicon technologies, including reduced complexity, the ability to optimize power/performance tradeoffs, lower operating voltage requirements, and improved gain and noise characteristics.   These advantages will become increasingly attractive as we migrate further into the world of low power, high performance portable electronic devices.

 

This entry was posted in Coventor Blog. Bookmark the permalink.

Comments are closed.