Lithography challenges threaten the cost benefits of IC scaling

By David Fried
Tech Design Forum

Will we be able to engineer another technology node that brings the usual cost and area savings without EUV lithography? I have serious doubts.

EUV lithography was supposed to be ready for the 45nm process node, and was then delayed until 32nm and later, 22nm. Today, major semiconductor companies are continuing to develop their offerings. Some will use the upcoming IEDM to detail their 1xnm processes, developed despite the lack of EUV’s patterning capabilities.

Why the delay with EUV? The story has been told many times: a combination of complex electro-optics, problems with the power of the illumination source, resist sensitivity and defectivity. The list of EUV challenges is long, but the summary is short: it’s not ready yet!

So, we embark on another round of process development, into the 10nm node, with the same lithography systems we’ve been using since 45nm: 193nm immersion, capable of numerical apertures around 1.35. The lithographers have pulled many tricks, known as resolution enhancement techniques (RETs), out of their bags. New types of masks, new polarizations of the source illuminators, the most complex model-based optical proximity corrections on the mask patterns have all been essential to maintain 2D scaling with 193nm light. But the physics of that 193nm system fundamentally limits the 1D pitch of single exposure printing to roughly 72nm. With 10nm technologies pushing pitches down towards the 50s, meeting the challenge will take much more than just another set of RET innovations.

Two “double-patterning” techniques are emerging to tackle the patterning issue, particularly for Back End of Line (BEOL) integration, where fundamental pitches are often tighter than at the Front End of Line (FEOL), and high aspect ratios and damascene integration pose additional process challenges. This paper outlines how each of these techniques works, their potential advantages and limitations. But despite the energy and ingenuity that has gone into developing these responses to the lack of EUV, the costs associated and the yield and reliability risks from process variation will prevent many companies from achieving the typical economic advantages of scaling.

Read more at: http://www.techdesignforums.com/practice/technique/lithography-challenges-1xnm-threaten-scaling/

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