By: Benjamin Vincent, Ph.D., Staff Engineer, Semiconductor Process & Integration
Engineering decisions are always data-driven. As scientists, we only believe in facts and not in intuition or feelings.
At the manufacturing stage, the semiconductor industry is eager to provide data and facts to engineers based upon metrics such as the quantity of wafers produced per hour and sites/devices tested on each of those wafers. The massive quantity of data generated in semiconductor manufacturing can provide facts that engineers can use to make immediate and accurate decisions, such as how they might correct any excursion or yield drift. Data exists, so life is (kind of…) easy! read more…
Tagged 2018 SPIE Advanced Lithography Conference, 5 nm, 5 nm Semiconductor Node, FSAV, Fully Self-Aligned Via, imec, Patterning Yield, SAB, SAQP, Self-Aligned Blocks, Self-Aligned Quadruple Patterning, SEMulator3D
New in SEMulator3D 7.0: Powerful new process and device simulation capabilities
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Coventor Adds Device Analysis Capabilities to SEMulator3D 7.0
New Features Enable SEMulator3D Version 7.0 to Address Both Process Modeling and Device Analysis for Better Insight into Advanced Semiconductor Technology Development
CARY, NC– February 28, 2018 – February 26, 2018 – Coventor, Inc., a Lam Research Company, the leading supplier of design automation solutions for semiconductor devices and micro-electromechanical systems (MEMS), today announced the availability of SEMulator3D® 7.0 – the newest version of its semiconductor virtual fabrication platform. With added features, performance improvements, and a new Device Analysis capability, SEMulator3D 7.0 addresses both process and device simulation while lowering the barriers to advanced semiconductor technology development. The new Device Analysis capability enables seamless understanding of how process changes, process variability, and integration schemes directly impact transistor device performance. read more…
Tagged 3D NAND, Coventor, device analysis, FinFET, FinFET Technology, FinFET transistor performance, lithography, lithography modeling, multi-patterning, NAND, Netlist, Netlist Extraction, Press release, Process Development, Process Integration, Process Modeling, Process Simulation, Process Variability, Process variation, semiconductor patterning, semiconductor process flow, semiconductor process modeling, semiconductor process variation, SEMulator 3D, SEMulator3D, SPICE simulation, TCAD, transistor device performance, transistor IV curves, transistor performance, virtual fabrication
By: Chris Welham, Senior Manager, MEMS Applications Engineering
A Section of a MEMS Microphone Model
Here at Coventor, we are seeing a lot of interest in simulating noise, particularly for condenser microphones. With any transducer noise reduction is always a plus, and with microphones there are two specific applications that need low noise. One is where the microphone is positioned away from the sound source, such as in video calling or when using voice commands with tablet computers. The other is where multiple microphones are positioned in an array, to detect the direction of incoming sound or for noise canceling applications. read more…
Tagged Johnson-Nyquist noise, MEMS, MEMS Condenser Microphone, mems design, MEMS Design Software, mems microphone, MEMS Noise Modeling, mems simulation, MEMS technology, MEMS+, Noise modeling
By: Chris Welham, Sr. Manager, MEMS Applications Engineering
Conference dinner view of the life-size outlines of the Titanic and Olympic main deck’s, illuminated by blue light
How are MEMS and Large Ships Alike?
MEMS 2018 was held in Belfast, Northern Ireland this year, on the site where the RMS Titanic was built. On exhibit was the SS Nomadic, a tender used to transfer mail and passengers to the RMS Titanic and her sister ship RMS Olympic. Passing by the SS Nomadic on the way to the conference dinner, I noticed the riveted plates from which the tender was built. These riveted plates reminded me of the finite element plate models used in the MEMS+ module of CoventorMP, which can also be joined to other elements using “connectors” or “nodes” rather than rivets. read more…
By: Michael Hargrove, SP&I Engineer
If my memory serves me well, it was at the 1989 Device Research Conference where the potential merits of SOI (Silicon on Insulator) technology were discussed in a heated evening panel discussion. At that panel discussion, there were many advocates for SOI, as well as many naysayers. I didn’t really think more about SOI technology until the mid-nineties, when I was sitting in a meeting where the first SOI device data was being presented in the hallowed halls of IBM. The data was incredibly scattered and my thinking was “this technology is going nowhere!” The purported performance advantage was stated to be ~35%, simply due to the capacitance reduction (no longer did the bottom junction capacitance play a role) and the speed advantages of stacked devices in a NAND circuit. It all sounded great, but in the mid-nineties, the data simply didn’t support it. Nonetheless, the SOI advocates pursued their beloved technology, and the rest is history. SOI technology has been part of IBM’s main stream high-performance technology base through the 14nm node, including FinFETs on SOI. read more…
Coventor recently sponsored an expert panel discussion at IEDM 2017 to discuss how we might advance the semiconductor industry into the next generation of technology. The panel discussed alternative methods to solve fundamental problems of technology scaling, using advances in semiconductor architectures, patterning, metrology, advanced process control, variation reduction, co-optimization and new integration schemes. Our panel included Rick Gottscho, CTO of Lam Research; Mark Dougherty, vice president of advanced module engineering at GlobalFoundries; David Shortt, technical fellow at KLA-Tencor; Gary Zhang, vice president of computational lithography products at ASML; and Shay Wolfling, CTO of Nova Measuring Instruments.
L-R: Ed Sperling (moderator), Shay Wolfling, Rick Gottscho, Mark Dougherty, Gary Zhang, David Shortt
Tagged 10NM, 2NM, 3D NAND, 3D XPOINT, 3NM, 5NM, 7NM, ASML, BEOL, DRAM, ETCH, EUV, FINFETS, GATE-ALL-AROUND FETS, GLOBALFOUNDRIES, INSPECTION, KLA-TENCOR, LAM RESEARCH, lithography, METROLOGY, Moore's Law, MRAM, NANOSHEETS, NOVA MEASURING INSTRUMENTS, PHASE-CHANGE MEMORY, RERAM, RESISTANCE, STRESS, STT-RAM, THIN FILMS, VON NEUMANN ARCHITECTURE