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Coventor in the News – Silicon Photonics

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Coventor in the News

Photonics in Silicon R&D Toward Tb/s

By Ed Korczynski, Sr. Technical Editor, Semiconductor Manufacturing & Design

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The client:server computing paradigm colloquially referred to as the “Cloud” results in a need for extremely efficient Cloud server hardware, and from first principles the world can save a lot of energy resources if servers run on photonics instead of electronics. Though the potential for cost-savings is well known, the challenge of developing cost-effective integrated photonics solutions remains. Today, discrete compound-semiconductor chips function as transmitters, multiplexers (MUX), and receivers of photons, while many global organizations pursue the vision of lower-cost integrated silicon (Si) photonics circuits.

Work on photonics chips—using light as logic elements in an integrated circuit—built in silicon (Si) has accelerated recently with announcements of new collaborative research and development (R&D) projects. Leti, an institute of CEA Tech, announced the launch of a European Commission Horizon 2020 “COSMICC” project to enable mass commercialization of Si-photonics-based transceivers to meet future data-transmission requirements in data centers and super computing systems.

The Leti-coordinated COSMICC project will combine CMOS electronics and Si-photonics with innovative fiber-attachment techniques to achieve 1 Tb/s data rates. These scalable solutions will provide performance improvement an order of magnitude better than current VCSELs transceivers, and the COSMICC-developed technology will address future data-transmission needs with a target cost per bit that traditional wavelength-division multiplexing (WDM) transceivers cannot meet. The project’s 11 partners from five countries are focusing on developing mid-board optical transceivers with data rates up to 2.4 Tb/s with 200 Gb/s per fiber using 12 fibers. The devices will consume less than 2 pJ/bit. and cost approximately 0.2 Euros/Gb/s.

Figure 1: Schematic of COSMICC on-board optical transceiver at 2.4 Tb/s using 50 Gbps/wavelength, 4 CWDM wavelengths per fiber, 12 fibers for transmission and 12 fibers for reception. (Source: Leti)

Figure 1: Schematic of COSMICC on-board optical transceiver at 2.4 Tb/s using 50 Gbps/wavelength, 4 CWDM wavelengths per fiber, 12 fibers for transmission and 12 fibers for reception. (Source: Leti)

A first improvement will be the introduction of a silicon-nitride (SiN) layer that will allow development of temperature-insensitive MUX/DEMUX devices for coarse WDM operation, and will serve as an intermediate wave-guiding layer for optical input/output. The partners will also evaluate capacitive modulators, slow-wave depletion modulators with 1D periodicity, and more advanced approaches. These include GeSi electro-absorption modulators with tunable Si composition and photonic crystal electro-refraction modulators to make micrometer-scale devices. In addition, a hybrid III-V on Si laser will be integrated in the SOI/SiN platform in the more advanced transmitter circuits.

Meanwhile in the United States, Coventor, Inc. is collaborating with the Massachusetts Institute of Technology (MIT) on photonics modeling. MIT is a key player in the AIM Photonics program, a federally funded, public-private partnership established to advance domestic capabilities in integrated photonic technology and strengthen high-tech U.S.-based manufacturing. Coventor will provide its SEMulator3D process modeling platform to model the effect of process variation in the development of photonic integrated components.

“Coventor’s technical expertise in predicting the manufacturability of advanced technologies is outstanding. Our joint collaboration with Coventor will help us develop new design methods for achieving high yield and high performance in integrated photonic applications,” said Professor Duane Boning of MIT. Boning is an expert at modeling non-linear effects in processing, many years after working on the semiconductor industry’s reference model for the control of chemical-mechanical planarization (CMP) processing.

—E.K.

See original article here

 

 

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IEEE WMED 2017 – April 21, 2016, Boise, ID

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2017 IEEE Workshop on Microelectronics and Electron Devices – WMED 2017

SPIE Advanced Lithography Symposium 2017 – February 26th-March 2, 2017, San Jose, CA

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SEE US AT BOOTH 306

Semiconductor Process and Integration Engineer – South Korea

Semiconductor Process and Integration Engineer – South Korea

We are seeking a BS/MS/PhD-level engineer who has experience and expertise in semiconductor process integration and fabrication. You will work with leading semiconductor companies to implement our virtual fabrication solution for their most advanced development programs, including 10nm CMOS technology and beyond! You will collaborate with the Semiconductor Process & Integration team in the Office of the CTO, along with our highly skilled software development team, to create integration and modeling solutions for industry-critical manufacturing challenges. Our tight-knit team of creative engineers is critical in leading customers into the methodology of virtual fabrication.

This is a hands-on engineering position, requiring proficiency in full flow semiconductor process integration, as well as strong communication and presentation skills. Your title, level of responsibility, creative freedom and salary will be commensurate with your education and experience.

Location: South Korea. This position requires residency in South Korea with a substantial amount of time at customer sites in South Korea. Work is expected to be partly based at customer/partner sites. Travel is expected.

Required Qualifications:

Education: Bachelor’s degree required, Master’s degree preferred, in related fields of Electrical Engineering, Chemical Engineering, Materials Science or Applied Physics.

Experience: Semiconductor Technology and Processing education and experience is required. Relevant employment experience in the semiconductor industry is required.

Skills: Semiconductor Processing and Integration, Semiconductor Device Physics (preferred), Computer-Aided Design (CAD) and Modeling, Python scripting language, Technical Writing , Communication and Presentation.

If you are interested in this opportunity and you are authorized to work in South Korea, e-mail your cover letter and CV in English to job1826@coventor.com.

About Coventor:

Coventor, Inc. (www.coventor.com) is the global market leader in virtual fabrication solutions for semiconductor technologies and design automation solutions for microelectromechanical systems (MEMS). Coventor serves a worldwide customer base of integrated device manufacturers, independent foundries, equipment makers, and R&D organizations that develop semiconductor and MEMS technologies for consumer, automotive, aerospace, industrial, and defense uses. Coventor’s predictive modeling tools and expertise enable its customers to dramatically reduce silicon learning cycles, giving them a time-to-market advantage and reducing technology development costs. The company is headquartered in Cary, NC and has offices in Waltham, MA; Silicon Valley, CA; Tokyo, Japan; Hsinchu, Taiwan; and Paris, France.

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Semiconductor Process and Integration Engineer – Taiwan

Semiconductor Process and Integration Engineer – Taiwan

We are seeking a BS/MS/PhD-level engineer who has experience and expertise in semiconductor process integration and fabrication. You will work with leading semiconductor companies to implement our virtual fabrication solution for their most advanced development programs, including 10nm CMOS technology and beyond! You will collaborate with the Semiconductor Process & Integration team in the Office of the CTO, along with our highly skilled software development team, to create integration and modeling solutions for industry-critical manufacturing challenges. Our tight-knit team of creative engineers is critical in leading customers into the methodology of virtual fabrication.

This is a hands-on engineering position, requiring proficiency in full flow semiconductor process integration, as well as strong communication and presentation skills. Your title, level of responsibility, creative freedom and salary will be commensurate with your education and experience.

Location: Taiwan. This position requires residency in Taiwan with a substantial amount of time at customer sites in Taiwan. Work is expected to be partly based at customer/partner sites. Travel is expected.

Required Qualifications:

Education: Bachelor’s degree required, Master’s degree preferred, in related fields of Electrical Engineering, Chemical Engineering, Materials Science or Applied Physics.

Experience: Semiconductor Technology and Processing education and experience is required. Relevant employment experience in the semiconductor industry is required.

Skills: Semiconductor Processing and Integration, Semiconductor Device Physics (preferred), Computer-Aided Design (CAD) and Modeling, Python scripting language, Technical Writing , Communication and Presentation.

If you are interested in this opportunity and you are authorized to work in Taiwan, e-mail your cover letter and CV in English to job1825@coventor.com.

About Coventor:

Coventor, Inc. (www.coventor.com) is the global market leader in virtual fabrication solutions for semiconductor technologies and design automation solutions for microelectromechanical systems (MEMS). Coventor serves a worldwide customer base of integrated device manufacturers, independent foundries, equipment makers, and R&D organizations that develop semiconductor and MEMS technologies for consumer, automotive, aerospace, industrial, and defense uses. Coventor’s predictive modeling tools and expertise enable its customers to dramatically reduce silicon learning cycles, giving them a time-to-market advantage and reducing technology development costs. The company is headquartered in Cary, NC and has offices in Waltham, MA; Silicon Valley, CA; Tokyo, Japan; Hsinchu, Taiwan; and Paris, France.

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BEOL Barricades: Navigating Future Yield, Reliability and Cost Challenges

By: David Fried, Ph.D., Chief Technology Officer, Semiconductor

Figure 1. M2-V1 process flow after (a) M2-L1 lithography, (b) M2-L2 litho, (c) V1 partial etch, (d) BLok open and (e) CuBS.

Coventor recently assembled an expert panel at IEDM 2016, to discuss changes to BEOL process technology that would be needed to continue dimensional scaling to 7 nm and lower. We asked our panelists questions such as: read more…

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Coventor’s Technology Roundtable at IEDM 2016

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Coventor Spearheads Discussion on Navigating Future Semiconductor Yield, Reliability and Cost Challenges

CARY, NC– December 6, 2016 – Coventor®, Inc., the leading supplier of automated software solutions for semiconductor devices and micro-electromechanical systems (MEMS), is sponsoring an advanced semiconductor technology panel on Tuesday, December 6 in San Francisco, California at the 2016 IEDM Conference. The panel is entitled “BEOL Barricades: Navigating Future Semiconductor Yield, Reliability and Cost Challenges”.

The panel discussion will explore major questions in advanced semiconductor development, including: read more…

SEMulator3D from Coventor Wins “Best of the West” Product Award

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Coventor’s Virtual Fabrication Platform Recognized for Its Significant Impact on Improving Electronics Manufacturing

CARY, NC– July 27, 2016 – Coventor®, Inc., the leading supplier of automated software solutions for semiconductor devices and micro-electromechanical systems (MEMS), today announced its SEMulator3D® 6.0 won the 2016 “Best of the West” award sponsored by Solid State Technology and SEMI at SEMICON West.  This prestigious industry award recognizes the product and technology developments that contributed the most significant improvements to the electronics manufacturing supply chain.  Coventor’s SEMulator3D was selected for the significant financial, scientific and social impact it has had on the industry.     read more…