MEMS+ 5.0 features expanded library of device structures; enhanced model export capability improves speed and visualization for MEMS + IC design
CARY, North Carolina – September 8, 2014 – Coventor®, Inc., the leading supplier of design automation software for micro-electromechanical systems (MEMS), today announced immediate availability of the latest version of its MEMS+® design solution for accelerating development of advanced MEMS devices and systems. MEMS+ 5.0 features an expanded modeling library to enable simulation of a greater variety of devices, with a particular focus on the unique challenges of micro-mirrors and piezo-electric devices. It also adds a new capability to create and export reduced-order models (ROMs) to the MATLAB® Simulink® environment from The MathWorks, Inc. to enable extremely fast and accurate non-linear simulations of MEMS-based systems. This supplements the existing capability to export ROMs in Verilog-A format for simulations of MEMS with electronics in widely used EDA simulators such as the Cadence® Spectre® circuit simulator.
We are seeking a dynamic, proactive software development engineer with a background in semiconductor technology or semiconductor software tools. In this key engineering position, you will lead the development of new software features related to our European research efforts in advanced CMOS (450mm/10nm/7nm). You will work closely with the Coventor semiconductor process technology team to understand the technical requirements of our partners, particularly metrology tool vendors and TCAD (Technology CAD) users. You will participate in the design and development of software interfaces to share our 3D structural models with other software tools.
This opening is a great opportunity for a strong coder with good communication skills. You will have the chance to work on a young, innovative product and to work closely with a collaborative, skilled team in both Europe and the USA. It is expected that responsibilities in this role will grow as Coventor’s European development team expands. Some travel is expected (less than 20%). You will report to the US-based Director of Semiconductor Software and R&D.
- Collaborate with our applications team to define requirements for new software features
- Lead the development effort to design and implement new features in C++ and Python
- Unit testing and bug fixing
- Help troubleshoot customer problems
- Provide input to and review documentation, tutorials, and user training materials
- PhD degree in computer science, electrical engineering, or a related field
- 6 or more years of professional software development experience, preferably related to semiconductor equipment, metrology or TCAD
- Expert-level coding skills in C++
- Strong aptitude for object oriented design
- Experience developing a 3D modeling software product, using either a 3D solid modeling kernel (ACIS, Parasolid, etc.), 3D mesh generation, or equivalent.
- Ability to clearly communicate technical concepts
- Must be able to read and understand technical articles and documentation written in English
- Must have a valid EU passport
- Experience with semiconductor metrology software, particularly model-driven metrology
- Experience with semiconductor TCAD modeling software
- Knowledge of semiconductor process technology
- Python coding skills
Salary, job title and responsibilities will be commensurate with experience. This opening is in Villebon sur Yvette (91), close to Paris. If you are interested in this opportunity and you are authorized to work in France, e-mail your resume in English to email@example.com
by Paul McLellan
At SEMICON last month, Rohit Pal of GlobalFoundries gave a presentation on their methodology for reducing process variation. It was titled Cpk Based Variation Reduction: 14nm FinFET Technology.
Capability indices such as Cpk is a commonly used technique to assess the variation maturity of a technology. It looks at a given parameter’s variability and compares it to 6 sigma. The higher the number the better, 1.33 should have the process yielding close to 100% (for that parameter) and 2 is the full 6 sigma. Using Cpk makes it easy to track metrics to assess variation improvement for a technology. They can also be used as a gating item for technology milestone achievement. However, it is not truly an absolute value, it is a function of the specification limits.
2014 International Conference on Simulation of Semiconductor Processes and Devices
September 9 – 11, 2014
Co-sponsored by The Japan Society of Applied Physics
Technical co-sponsored by The IEEE Electron Devices Society
This conference provides an opportunity for the presentation and discussion of the latest advances in modeling and simulation of semiconductor devices, processes, and equipment for integrated circuits.
By Steve Breit, Vice President Engineering
The CoventorWare 2014 release has been announced and is now available to customers. I presided over the first release of CoventorWare in 2001 and eight major releases since then with numerous updates in between. With each release, we added new capabilities, and capacity, speed, and accuracy improvements to address the ever more demanding requirements of our users. The new capabilities and performance improvements in each release are easy to talk about and receive all the glory. In this respect, CoventorWare 2014 is no different: the highlights are covered in our press release and a What’s New page elsewhere on our site; I won’t repeat them here. Instead, I want to talk about the steady improvements in the usability, robustness and quality of the software and the documentation. These improvements aren’t as glamorous as the shiny new stuff, but I believe they really matter to users. Our quality assurance team and our documentation team deserve a lot of credit for these improvements. They’re the unsung heroes of CoventorWare.
by Pawan Fangaria
We all know that Technology Computer Aided Design (TCAD) simulations are essential in developing processes for semiconductor manufacturing. From the very nature of these simulations (involving physical structure and corresponding electrical characteristics of a transistor or device), they are predominantly finite-element based simulations with complex set of equations to be solved which require large computation, thus increasing simulation time exponentially with the size of the device. It was okay for earlier generations of semiconductor technology nodes to rely on transistor or small cell level process and characterization to develop large designs which were then verified through several build-and-test cycles through actual foundries. However, for today’s nanometer technology nodes and large, complex, high-density designs with complex transistor structures like FinFET and others which exhibit excessive variability in manufacturing, it’s clear that the same old methodology will no longer be effective. . Along with the technology, the economics of chip manufacturing and marketing has become equally pressing, needing substantial reduction in P/Q ratio and very high TAT in order take advantage of ever shrinking windows of opportunity.