By Francoise von Trapp
3D In-Depth, EDA Tools
I don’t usually write about MEMS. But every once in a while, when MEMS (stands for micro-electromechanical systems) touches anything to do with 3D integration, usually at the system-level, I might veer slightly out of my comfort zone to interview a MEMS supplier about their latest developments. I find it’s a good way to learn about the synergies and to cross-pollinate information. Today was one of those days. I interviewed Steve Breit, PhD, VP of Engineering, Coventor, supplier of design automation software for MEMS and semiconductor applications. Breit reminded me that through silicon via technology (TSV), which is critical for 3D IC, owes a debt to MEMS. He’s right about that. So I figure a nod to MEMS now and again on 3D InCites isn’t out of place.
Breit briefed me on the company’s latest version of its MEMS+ modeling environment for accelerated development of advanced MEMS devices and systems, and what the improvements mean for ASIC designers who need to integrate MEMS devices into their system design.
Gunar Lorenz, PhD
Director, System Level Simulation
We just rolled out MEMS+ 5.0 with lots of new capabilities for our users. I discussed some of the new features, support of scanning mirrors in particular, in a previous post. This time I would like to focus on the new capabilities for exporting reduced order models (ROMs) of MEMS devices that system engineers can place in their Simulink schematics and IC designers can place in their circuit schematics.
Before getting into the technical stuff, allow me to provide some motivation. To design the control and signal processing electronics that go around every MEMS device, system engineers usually work in Simulink while circuit designers work in schematic entry tools such as Cadence Virtuoso. There’s a MEMS block in their flow diagram or schematic with an underlying model that captures the coupled electromechanical behavior of the MEMS device. It’s common practice to “hand craft” the MEMS behavioral model, but hand crafted models have many shortcomings: they’re usually over simplified, capturing only one degree of freedom and omitting nonlinear effects. Furthermore, it’s difficult to keep hand crafted models in sync with evolving device designs. All of these shortcomings can be avoided by using ROMs exported from MEMS+ instead of hand-crafted models.
MEMS+ 5.0 features expanded library of device structures; enhanced model export capability improves speed and visualization for MEMS + IC design
CARY, North Carolina – September 8, 2014 – Coventor®, Inc., the leading supplier of design automation software for micro-electromechanical systems (MEMS), today announced immediate availability of the latest version of its MEMS+® design solution for accelerating development of advanced MEMS devices and systems. MEMS+ 5.0 features an expanded modeling library to enable simulation of a greater variety of devices, with a particular focus on the unique challenges of micro-mirrors and piezo-electric devices. It also adds a new capability to create and export reduced-order models (ROMs) to the MATLAB® Simulink® environment from The MathWorks, Inc. to enable extremely fast and accurate non-linear simulations of MEMS-based systems. This supplements the existing capability to export ROMs in Verilog-A format for simulations of MEMS with electronics in widely used EDA simulators such as the Cadence® Spectre® circuit simulator.
by Paul McLellan
At SEMICON last month, Rohit Pal of GlobalFoundries gave a presentation on their methodology for reducing process variation. It was titled Cpk Based Variation Reduction: 14nm FinFET Technology.
Capability indices such as Cpk is a commonly used technique to assess the variation maturity of a technology. It looks at a given parameter’s variability and compares it to 6 sigma. The higher the number the better, 1.33 should have the process yielding close to 100% (for that parameter) and 2 is the full 6 sigma. Using Cpk makes it easy to track metrics to assess variation improvement for a technology. They can also be used as a gating item for technology milestone achievement. However, it is not truly an absolute value, it is a function of the specification limits.
2014 International Conference on Simulation of Semiconductor Processes and Devices
September 9 – 11, 2014
Co-sponsored by The Japan Society of Applied Physics
Technical co-sponsored by The IEEE Electron Devices Society
This conference provides an opportunity for the presentation and discussion of the latest advances in modeling and simulation of semiconductor devices, processes, and equipment for integrated circuits.
By Steve Breit, Vice President Engineering
The CoventorWare 2014 release has been announced and is now available to customers. I presided over the first release of CoventorWare in 2001 and eight major releases since then with numerous updates in between. With each release, we added new capabilities, and capacity, speed, and accuracy improvements to address the ever more demanding requirements of our users. The new capabilities and performance improvements in each release are easy to talk about and receive all the glory. In this respect, CoventorWare 2014 is no different: the highlights are covered in our press release and a What’s New page elsewhere on our site; I won’t repeat them here. Instead, I want to talk about the steady improvements in the usability, robustness and quality of the software and the documentation. These improvements aren’t as glamorous as the shiny new stuff, but I believe they really matter to users. Our quality assurance team and our documentation team deserve a lot of credit for these improvements. They’re the unsung heroes of CoventorWare.