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Delivering the Next 5 Years of Semiconductor Technology

New, advanced semiconductor processing and architectural technologies take years to perfect and put into production. In the meantime, semiconductor customers continue to demand faster, smaller and higher functioning devices. Semiconductor manufacturers need to decide whether (and when) to jump to the next generation of devices and production technologies, weighing the risk and benefit of bringing the next processing and architecture technologies to market.

A recent example of this type of risk analysis can be found in the gradual plans by foundries to adopt EUV technology. EUV technologies will reduce current requirements for multi patterning and (eventually) improve yields. However, EUV technology has many technological hurdles, including mask defects, CD uniformity, and production rate and yield issues. Billions of dollars have been invested in EUV development, yet no foundry is currently using the technology in production.

Could we extend existing technology concepts to deliver the next generations of semiconductor scaling, and avoid or defer the risk of jumping to next generation device and production technologies? Or, does the industry need paradigm-shifting technologies to reach these goals? Is there a way that we squeeze additional angstroms out of existing process and technology elements? Can we use variation reduction and process control to create the next few generations of semiconductor scaling? Or, do we simply need entirely new processes and architectures to reach these difficult goals?

There might be an entire node of scaling available from variation reduction, with numerous opportunities for variation reduction in advanced technology development. Our ability to detect, measure and characterize variability issues will be critical in variation reduction, along with process optimization and co-optimization strategies and challenges. Process controls are a key factor in being able to reduce process variability and to scale effectively.

If you are interested in exploring this topic further, we invite you to attend a complimentary seminar sponsored by Coventor in San Francisco on December 5, 2017, entitled “Everything is Under Control:  Delivering the Next 5 Years of Semiconductor Technology”. The seminar will be moderated by Ed Sperling, Editor in Chief of Semiconductor Engineering. Leading semiconductor industry panelists will discuss alternative methods to solve fundamental problems of technology scaling, and review techniques and strategies that might extend the lifetime of the latest technologies and propel us into the future. They will explore the latest advances in semiconductor architectures, patterning, metrology, advanced process control, co-optimization and integration. If you are unable to attend the seminar, keep your eye on future issues of Semiconductor Engineering to view a summary of the discussion.

To pre-register for the complimentary panel discussion, click here.

SEMulator3D Honored as UBM ACE Award Finalist

For Immediate Release
For more information, contact:
Toni Sottak
(408) 876-4418
toni@wiredislandpr.com

SEMulator3D Honored as UBM ACE Award Finalist

Coventor’s Virtual Fabrication Platform Recognized for Significantly Improving Electronics Manufacturing

CARY, NC– November 17, 2017 – Coventor®, Inc. a Lam Research Company and leading supplier of virtual fabrication solutions for semiconductor and micro-electromechanical systems (MEMS) devices, today announced its 3D virtual fabrication platform, SEMulator3D®, has been named a finalist in UBM’s annual ACE Awards competition.

The ACE (Annual Creativity in Electronics) Awards, in partnership with EE Times and EDN, showcase the best of the best in today’s electronics industry, including the hottest new products, start-up companies, design teams, executives, and more. ACE finalists and winners are hand selected by a panel of EE Times and EDN editors as well as independent judges from the across the industry. read more…

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Overlay Challenges On The Rise

By MARK LAPEDUS

The overlay metrology equipment market is heating up at advanced nodes as the number of masking layers grows and the size of the features that need to be aligned continue to shrink.

Both ASML and KLA-Tencor recently introduced new overlay metrology systems, seeking to address the increasing precision required for lines, cuts and other features on each layer. At 10/7nm, there may be 80 or more masking layers, versus 40 at 28nm. And if those layers are not precisely measured, the features being patterned, deposited and etched may not line up from one layer to the next.

read the full article here.

Technical Tidbits from IWLPC and MSEC 2017

By Francoise von Trapp

It’s been a busy few weeks for me as I attended both the International Wafer Level Packaging Conference (IWLPC), October 24-26, 2017 at the DoubleTree in San Jose and SEMI-MSIG’s MEMS and Sensors Executive Congress, October 31-Nov. 2, at the Hayes Mansion in San Jose. In addition to taking in some great keynotes and technical sessions, I had the opportunity to meet with several companies to find out what’s new.

read the full article here.

Lam’s Coventor Buy Boosts MEMS Manufacturing

By R. Colin Johnson

SAN JOSE, Calif.—Why did Lam Research, a semiconductor fab equipment supplier, acquire Coventor, a software house hawking software to design microelectromechanical system (MEMS) chips and sub-10 nanometer semiconductors such as 3D finFETs?

Analysts fully expected for Coventor to be absorbed by Lam Research, only to surface as a Lam software offering. But at SEMI’s MEMS & Sensor Executive Congress 2017 (MSEC) here the companies reported that they are staying in separate headquarters, depending more the synergy of co-designing hardware for software and visa versa to give them a competitive edge over the competition.

read the full article here.

半導体プロセス・インテグレーションエンジニア – 日本

半導体プロセス・インテグレーションエンジニア – 日本

半導体プロセスインテグレーションと製造に経験と専門知識を持つBS / MS / PhDレベルのエンジニアを探しています。 大手の半導体企業と協力し、ロジック、DRAM、そして、NANDフラッシュ技術を含む開発プログラムのバーチャル製造ソリューションを実現、提供します。 高度に熟練したソフトウェア研究開発チームと共に、セミコンダクタープロセス・インテグレーションチームと協力して、工程及び製造上の重要な課題を解決するインテグレーションモデリングソリューションを顧客に提供します。

これは実践的なエンジニアリングのポジションであり、半導体プロセスインテグレーションとスクリプトプログラミング(TCLやPython等)、優れたコミュニケーションとプレゼンテーションのスキルを必要とします。

勤務地:日本(神奈川県新横浜、又は、三重県四日市)。 日本の顧客拠点に一定期間の滞在が必要な場合もあります。

必要資格:

教育:電気工学、化学工学、材料科学または応用物理学の関連分野で、学士号必須、修士号または博士号は優遇。

経験:半導体デバイス製造プロセスの開発と構築、半導体デバイスとプロセスのモデリング、その他の半導体産業に関連する雇用の経験が必要です。

スキル:半導体プロセスインテグレーション、半導体デバイスとプロセスのモデリングやシミュレーション(TCAD)、TCLやPython等スクリプト言語、Linux OS環境、テクニカルライティング、実用レベルの英語、コミュニケーションとプレゼンテーション。

 

このポジションに興味があり、日本で働く資格がある場合は、英文のカバーレターと履歴をjob1826@coventor.comに電子メールで送ってください。

Semiconductor Process and Integration Engineer – Japan

Semiconductor Process and Integration Engineer – Japan

We are seeking a BS/MS/PhD-level engineer who has experience and expertise in semiconductor process integration and fabrication. You will work with leading semiconductor companies to implement our virtual fabrication solution for their most advanced development programs, including advanced CMOS, DRAM and 3D NAND Flash technologies. You will collaborate with the Semiconductor Process & Integration team along with our highly skilled software development team, to create integration and modeling solutions for industry-critical manufacturing challenges.

This is a hands-on engineering position, requiring proficiency in full flow semiconductor process integration and script programming (python) as well as strong communication and presentation skills. Your title, level of responsibility, creative freedom and salary will be commensurate with your education and experience.

Location: Japan(Shin-Yokohama or Yokkaichi city). This position requires residency in Japan with a substantial amount of time at customer sites in Japan. Work is expected to be partly based at customer/partner sites. Travel is expected.

Required Qualifications:

Education: Bachelor’s degree required, Master’s degree or Ph-D preferred, in related fields of Electrical Engineering, Chemical Engineering, Materials Science or Applied Physics.

Experience: Semiconductor Technology and Processing education and experience is required. Relevant employment experience in the semiconductor industry is required.

Skills: Semiconductor Processing and Integration, Semiconductor Device Physics (preferred), Computer-Aided Design (CAD) and Modeling, Python scripting language, Technical Writing , Fluency in English and Japanese, Communication and Presentation (spoken and written).

If you are interested in this opportunity and you are authorized to work in Japan, e-mail your cover letter and CV in English to job1865@coventor.com .

MEMS Market Shifting

By Ed Sperling

The MEMS sector is beginning to look more promising, bolstered by new end-market demand and different packaging options that require more advanced engineering, processes and new materials. All of this points to higher selling prices, which are long overdue in this space.

For years, the market for microelectromechanical systems was populated by too many companies vying for too few opportunities. Some devices became commoditized to the point where costs failed to keep up with selling price reductions. Even in the more specialized and higher-margin fringes of this segment, such as MEMS-based microphones and speakers, market sizes were too small to support more than a handful of smaller companies.

read the full article here.