IMEC Partner Technical Week Review
By: Aurélie Juncker, Semiconductor Process & Integration Engineer
a. Fully aligned Via with Cu recess approach – Gayle Murdoch, b. STT-RAM – Davide Crotti, c. N10 Supernova2 process – Matt Gallagher
In March 2016, Coventor was invited to the biannual Partner Technical Week (PTW) at IMEC in Leuven, Belgium. IMEC, a world-leading research group in nanotechnology, organizes their Partner Technical Week every 6 months to present scientific results to their partners. During this week, a number of specialists from IMEC’s many partner companies also discuss their progress in areas related to IMEC’s research. This event brings together a large number of engineers who are specialists in their domain, and provides an interesting forum to leverage the scientific knowledge gained by IMEC and its partners. read more…
Tagged 7 nm, BEOL, Coventor, DOE, DUV, ETCH, EUV, FEOL, i193, lithography, misalignment, multi-patterning, N7, patterning, virtual fabrication
By Luke Collins, Tech Design Forum
Coventor has updated its SEMulator3D virtual fabrication tool so it can extract predicted resistance and capacitance values from its models. The analysis tool could be used to speed up the availability of early PDKs for rapidly evolving processes.
SEMulator3D abstracts IC manufacturing steps into behavioural models, so that it can simulate a a whole process in a ‘virtual fab’. Because the process steps are modeled using behavioural abstractions, rather than full physics, it becomes practical to run multiple options to explore how variations in each step will affect overall outcomes.
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By R. Colin Johnson, EE Times
LAKE WALES, Fla.—What began as a microelectromechanical systems (MEMS) 3-D design tool has transformed into a 3-D semiconductor design tool which has accordingly added Electrical Analytics to the latest version six of Coventor’s SEMulator3D. See Coventor’s SEMulator3D at the Design Automation Conference (DAC 2016, Austin, Texas, June 5-9), booth 321.
Besides chip designers—now its biggest user segment—are systems designers who, the company claims, make up its fastest growing customer segment. System designers are most interested in how process variations impact their product’s yield robustness, according to David Fried, chief technology officer (CTO) of semiconductors for Coventor.
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Coventor’s Virtual Fabrication Platform Addresses Increasingly Complex Semiconductor Process Design Challenges
CARY, NC– June 6, 2016 – Coventor®, Inc., the leading supplier of automated software solutions for semiconductor devices and micro-electromechanical systems (MEMS), today announced the availability of SEMulator3D® 6.0 – the latest version of its semiconductor virtual fabrication platform. This new version further increases the accuracy of the process simulation, geometry and modeling of advanced semiconductor processes with new features, usability enhancements and a new add-on capability for electrical analysis. Along with SEMulator3D 6.0, Coventor is releasing an all-new SEMulator3D Electrical Analysis add-on component that allows seamless resistance and capacitance extraction directly from SEMulator3D process-predictive 3D models. read more…
By: Daniel Sieger, Lead Engineer, SEMulator3D Geometry and Michael Hargrove, Semiconductor Process & Integration Engineer
The SEMulator3D software platform has once again been updated and improved with significantly more features, making it the industry leader in semiconductor virtual fabrication. read more…
By Mark Lapedus
Semiconductor Engineering sat down to discuss the foundry business, memory, process technology, lithography and other topics with David Fried, chief technology officer at Coventor, a supplier of predictive modeling tools. What follows are excerpts of that conversation.
SE: Chipmakers are ramping up 16nm/14nm finFETs today, with 10nm and 7nm finFETs just around the corner. What do you see happening at these advanced nodes, particularly at 7nm?
Fried: Most people are predicting evolutionary scaling from 14nm to 10nm to 7nm. It’s doubtful that we will see anything really earth-shattering in these technologies. And so, a lot of the challenges come down to patterning. We are going to see multi-patterning schemes really take hold at more levels. For example, the fins are now based on self-aligned double patterning. People will move into self-aligned quad patterning. The gates are maybe self-aligned double. Now, they will move into self-aligned quad. So, that’s going to be a big expense, because each level is going to have multiple passes and multiple cuts.
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Tagged 10NM, 3D NAND, 5NM, ATOMIC-LEVEL VARIABILITY, BEOL, Coventor, DEPOSITION, Directed Self Assembly, DSA, ETCH, EUV, III-V MATERIALS, INTEL, lithography, LOW-K DIELECTRICS, MRAM, multi-patterning, NANOWIRE FETS, RC DELAY, RERAM, SADP, TSMC
By: Stephen Breit, VP of Engineering
I recently gave an invited talk at the IEEE Inertial Sensors 2016 symposium that discussed the future of commodity MEMS inertial sensor design and manufacturing. Inertial sensors comprise one of the fastest growing and most successful segments of the MEMS market. read more…