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Inside Process Technology

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By Mark Lapedus

Semiconductor Engineering sat down to discuss the foundry business, memory, process technology, lithography and other topics with David Fried, chief technology officer at Coventor, a supplier of predictive modeling tools. What follows are excerpts of that conversation.

SE: Chipmakers are ramping up 16nm/14nm finFETs today, with 10nm and 7nm finFETs just around the corner. What do you see happening at these advanced nodes, particularly at 7nm?

Fried: Most people are predicting evolutionary scaling from 14nm to 10nm to 7nm. It’s doubtful that we will see anything really earth-shattering in these technologies. And so, a lot of the challenges come down to patterning. We are going to see multi-patterning schemes really take hold at more levels. For example, the fins are now based on self-aligned double patterning. People will move into self-aligned quad patterning. The gates are maybe self-aligned double. Now, they will move into self-aligned quad. So, that’s going to be a big expense, because each level is going to have multiple passes and multiple cuts.

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The Future of MEMS Sensor Design and Manufacturing

By:  Stephen Breit, VP of Engineering

I recently gave an invited talk at the IEEE Inertial Sensors 2016 symposium that discussed the future of commodity MEMS inertial sensor design and manufacturing. Inertial sensors comprise one of the fastest growing and most successful segments of the MEMS market. read more…

Will directed self-assembly pattern 14nm DRAM?

By: Mattan Kamon, PhD., Distinguished Technologist, R&D, Coventor

Matt's March 2016 Blog Graphic

But first, more generally, will directed self-assembly (DSA) join Extreme Ultraviolet (EUV) Lithography and next generation multi-patterning techniques to pattern the next memory and logic technologies?  Appealing to the wisdom of crowds, the organizers of the 2015 1st International DSA symposium recently surveyed the attendees, and nearly 75% believed DSA would insert into high volume manufacturing within the next 5 years, and nearly 30% predicted insertion within the next 2 years.   What is gating insertion?  The crowd rated defectivity as the most critical issue facing DSA.  This fact adds weight to memory being the first to be patterned with DSA.  This is because, as Roel Gronheid from IMEC pointed out last month at the SPIE Advanced Lithography conference [1], memory chips can tolerate single failing cells through redundancy and so can could tolerate higher defectivity in patterning (roughly 1 defect/cm2 compared to 0.01 defect/cm2 for logic).  Defectivity rates for DSA aren’t there yet (according to public information), but are rapidly approaching [2], [3]. read more…

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Multi-Beam Market Heats Up

se_logoBy Mark Lapedus

The multi-beam e-beam mask writer business is heating up, as Intel and NuFlare have separately entered the emerging market.

In one surprising move, Intel is in the process of acquiring IMS Nanofabrication, a multi-beam e-beam equipment vendor. And separately, e-beam giant NuFlare recently disclosed its new multi-beam mask writer technology.

As a result of the moves, the Intel/IMS duo and NuFlare will now race each other to bring multi-beam mask writers into the market. Still in the R&D stage, these newfangled tools promise to speed up the write times for next-generation photomasks, although there are still challenges to bring this technology into production.

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New MEMS Design Contest Encourages Advances in MEMS Technology

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Industry leaders in EDA & foundry services collaborate with academia to explore future possibilities of CMOS/MEMS integration  

Dresden, Germany – March 16, 2016 – Jointly sponsored by Cadence Design Systems, Coventor, X-FAB and Reutlingen University, a new MEMS Design Contest is being launched at DATE 2016.  The objective of this contest is to encourage greater ingenuity with regard to the integration of MEMS devices and mixed-signal CMOS blocks.  To kick off the contest, an informative session will be held in the Exhibition Theatre on Thursday, March 17, 2016 from 14:00 to 17:30 and is open to all DATE attendees free of charge. read more…

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MEMS Grand Challenge Debuts

ee-timesBy R. Colin Johnson, EE Times

LAKE WALES Fla.—Simplfying and popularizing microelectromechanical system (MEMS) design is the goal of the MEMS Design Contest announced yesterday (March 16) at the conference titled Data Automation and Test in Europe (DATE 2016, March 15 to 17, Dresden, Germany). More specifically, the contest encourages chip designers to add MEMS blocks to a chip design, using tools designed for the purpose.

Sponsored by Cadence Design Systems, Coventor, X-FAB and Reutlingen University, the contest will feature a special process design kit (PDK) that the winners will use to fabricate their MEMS chip at X-Fab. If interested attend the DATE session Launch of the Worldwide MEMS Design Contest.

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7nm Lithography Choices

se_logoBy Mark Lapedus

Chipmakers are ramping up their 16nm/14nm logic processes, with 10nm expected to move into early production later this year. Barring a major breakthrough in lithography, chipmakers are using today’s 193nm immersion and multiple patterning for both 16/14nm and 10nm.

Now, chipmakers are focusing on the lithography options for 7nm. For this, they hope to use a combination of two technologies at 7nm—extreme ultraviolet (EUV) lithography, and 193nm immersion with multi-patterning.

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The Sensor Swarm Arrives

By Tom Kevan, Desktop Engineering

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It all started with smartphones and airbags. Design engineers began to integrate sensors in growing numbers into such systems to enable smarter performance. These applications mark the prelude to what Alberto Sangiovanni-Vincentelli, a professor at University of California, Berkeley, describes as a “sensory swarm” — a flood of heterogeneous sensors interfacing the cyber and physical worlds. By 2025, experts predict that the swarm could number as many as 7 trillion devices.

One of the first stages in the realization of this sensor-dominated world, the Internet of Things (IoT) requires technologies that can take on smaller form factors and operate on miserly power budgets. In their search to find sensing devices that can meet these requirements, designers have turned to micro-electromechanical systems, or MEMS. Before they can take full advantage of the miniaturization the technology offers and expand its role in the marketplace, engineers must be able to bridge the gaps between the MEMS, analog and digital design worlds. To do this, they will require a new set of tools.

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