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Engineering Software Quality Assurance Team Lead – Waltham, MA

Engineering Software Quality Assurance Team Lead – Waltham, MA

We are seeking a BS- or MS-level engineer with a strong interest in 3D modeling and simulation to lead a quality assurance team responsible for testing our advanced semiconductor virtual fabrication software. You will be responsible for coordinating the daily activities of our quality assurance team, which is embedded in a collaborative software development team that is following the Scrum development process. Through continuous engagement with developers, organizing test plans for new features and maintaining regression test suites, you will play a critical role in helping us deliver quality software for both the Windows and Linux platforms. This is an engineering position, not a managerial role, where your strong engineering knowledge will enable you to directly test the software in order to provide effective supervision of your team and valuable input to our software development team. Your compensation will be commensurate with your education and experience.

This regular, full-time position is located in our office in Waltham, MA. Coventor offers comprehensive benefits and is an EEO/AA Employer. You must be a current legal resident of the U.S. or have a valid U.S. visa to apply for this position. Please e-mail a cover letter and resume to job1838@coventor.com

Responsibilities

  • Supervise the daily activities of a team of software quality assurance engineers
  • Digest software specifications and organize plans for systematically testing new engineering functionality
  • Develop, execute and maintain verification test cases for both automatic and manual regression test suites
  • Understand the functionality of our semiconductor virtual fabrication environment
  • Actively participate in our Scrum-based agile development process
  • Submit defect reports and enhancement requests
  • Collaborate with software developers to isolate defects
  • Interact with the applications support team to define realistic test cases
  • Create examples and draft documentation for use in product documentation and marketing collateral

Required Qualifications

  • BS or MS in Electrical Engineering, Mechanical Engineering or a related discipline
  • At least 5 years of work experience as a quality assurance engineer of 3D engineering software such as CAD, CAE or TCAD tools
  • Detail oriented individual who enjoys systematically exploring software
  • Team oriented personality with excellent interpersonal skills
  • Excellent English communication skills (verbal and written)
  • Proficiency with Windows and/or Linux operating systems
  • Scripting skills in Python, MATLAB, or similar scripting language

Desirable Qualifications

  • Semiconductor technology and processing education and experience
  • Basic understanding of numerical modeling algorithms
  • Working knowledge of Agile methodology

Smart Systems Integration – March 11-12, 2015

Smart Systems Integration – March 11-12, 2015 – Copenhagen
International Conference and Exhibition

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Coventor will participate in a panel discussion on March 11, 2015 at 2:45pm, titled: “Towards a ‘Lego Brick Principle’ for Heterogeneous System Design Including MEMS and Electronic – Choose and Put Together – Fit?”

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Defect Evolution in 3D NAND Flash

by Sandy Wen, Semiconductor Process and Integration

3D NAND Flash has become a hot topic in non-volatile memory these days. While planar NAND flash is still going strong, it has been increasingly difficult to scale planar technology past the sub-20nm lengths and meet upcoming memory cell density and cost targets. In a different approach, Toshiba published early work on 3D NAND in 2007 [1] in which flash cells are stacked vertically to increase cell density. Since then, all major flash memory manufacturers have jumped aboard this train with their own flash architectures, and in 2013, Samsung became the first to ship “V-NAND” in the form of a solid state drive.
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2015 IEEE Workshop on Microelectronics and Electron Devices – March 20 2015 – Idaho, USA

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The Thirteenth Annual Workshop on Microelectronics and Electron Devices (WMED 2015). WMED 2015 will provide a forum for reviewing and discussing all aspects of microelectronics including processing, electrical characterization, design, and new device technologies.

Friday, March 20, 2015
Jordan and Simplot Ballrooms
Student Union Building
Boise State University
1910 University Drive
Boise, Idaho 83725

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IEEE ISISS 2015 – March 23-26, 2015 – Hawaii

2nd Annual IEEE International Symposium on Inertial Sensors and Systems

Hupuna Beach Prince Hotel, Hawaii, USA

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IEEE ISISS 2015 will be a 4 day event with tutorials on Monday, March 23, and the symposium’s technical sessions on March 24-26.

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DTIP 2015 – Montpellier – France, 27 – 30 April 2015

DTIP 2015 – Montpellier – France, 27 – 30 April 2015
DTIP

DTIP is a symposium including two main Conferences: the CAD, Design and Test Conference devoted to the development of Computer-Aided Design (CAD) tools and design methodologies for MEMS and MOEMS, and the Microfabrication, Integration and Packaging Conference dedicated to the development of integration technologies and packaging for MEMS and MOEMS. Both conferences share common plenary talks including invited talks, panels and special sessions to allow close interaction between both communities.

Among others, the program features presentations from Zeiss, ST, imec, ESIEE, Politechnico di Torino and Thales. A special session on « Co-design for MEMS based Smart Systems » is organized by Gerold Schröpfer from Coventor, France.

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Chips Are Going 3D, DRC Needs to Go 3D Too

SemiWiki
by Paul McLellan
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The last paradigm shift in DRC was around 0.35um when designs got too large to handle as flat data, and hierarchical approaches were required. Back then the design rules themselves were not that complex, the explosion of data volume came from the complexity of the design itself. But each process node added more design rules intricacies and many new types of rules that needed to be checked.

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SPIE Advanced Lithography – February 22-26, 2015

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SPIE Advanced Lithography, February 22-26, 2015, in San Jose, CA.

Coventor will attend SPIE 2015, visit us at booth #205

San Jose Marriott and San Jose Convention Center
San Jose, California, United States
22 – 26 February 2015

SPIE is a highly regarded exhibition for the industry’s top semiconductor suppliers, integrators, and manufacturers. 61 exhibiting companies in 2014.

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