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The Smart Systems Integration Conference 2018 – April 11- 12, 2018, Dresden, Germany

 

The Smart Systems Integration Conference 2018

Paper at the conference: New Advancements in Using Statistical Models as Part of a Standard MEMS Design Flow

Author: Christine Dufour, Christof Hielscher

SEMICON China 2018 – March 14 – 16, 2018, Shanghai, China

SEMICON China 2018

2nd Electron Devices Technology and Manufacturing (EDTM) Conference 2018 – March 13-16, 2018, Kobe, Japan

IEEE EDTM 2018

SPIE Advanced Lithography Symposium 2018 – 25 February – 1 March, San Jose, CA

spie-2017-logo

 

SEE US AT BOOTH 323/325

Keynote Address: David Fried, “Equipment Intelligence: Process Control in 3D”

SEMICON Korea 2018 – January 30 – February 2, 2018, Coex, Seoul

SEMICON Korea 2018

IEEE International Conference on Micro Electro Mechanical Systems (MEMS 2018) – 21-25 January, 2018, Belfast, North Ireland

 

SEE US AT BOOTH 21

The Race To 10/7nm

By Mark Lapedus

Amid the ongoing ramp of 16/14nm processes in the market, the industry is now gearing up for the next nodes. In fact, GlobalFoundries, Intel, Samsung and TSMC are racing each other to ship 10nm and/or 7nm technologies.

The current iterations of 10nm and 7nm technologies are scaled versions of today’s 16nm/14nm finFETs with traditional copper interconnects, high-k/metal-gate and low-k dielectrics. In finFETs, the control of the current is accomplished by implementing a gate on each of the three sides of a fin.

read the full article here.

What drives SADP BEOL variability?

By: Michael Hargrove, Semiconductor Process & Integration Engineer

Until EUV lithography becomes a reality, multiple patterning technologies such as triple litho-etch (LELELE), self-aligned double patterning (SADP), and self-aligned quadruple patterning (SAQP) are being used to meet the stringent patterning demands of advanced back-end-of-line (BEOL) technologies.  For the 7nm technology node, patterning requirements include a metal pitch of 40nm or less. This narrow pitch requirement forces the use of spacer based pitch multiplication techniques. Unfortunately, these techniques have high process/lithography variability, which can severely impact RC and overall device performance.

read more…

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