Semiconductor Fabrication Module Optimization

by Pawan Fangaria

The growing process integration complexity at each technology node has increased development time and cost, and this trend looks to continue. There is a looming risk of delivering unrepeatable critical unit processes (or process modules) that would require revisiting development and manufacturing requalification or in severe cases a design re-spin. Below the 22nm process node, tremendous effort is necessary to meet process integration specifications with a yielding process that is robust in the face of unavoidable manufacturing variation.

In one of my earlier articles here, I talked about a quick and automated way to optimize the complex BEOL (Back-End-Of-Line) metallization process through the use of Virtual Fabrication provided by a state-of-the-art tool, SEMulator3D from Coventor. A BEOL metallization whitepaper illustrates the SEMulator3D platform capability to assist with process development and optimization. SEMulator3D is an extremely powerful Virtual Fabrication tool to perform all types of tasks related to complete semiconductor chip manufacturing process, including FEOL (Front-End-Of-Line), MOL (Middle-Of-Line) and BEOL processes, quickly at your desk.

As Virtual Fabrication becomes increasingly important to help development keep pace with Moore’s Law, the semiconductor design and fabrication community are eager to understand more about how to leverage this technology. In the most straightforward sense, this means replacing costly and lengthy iterations of build-and-test learning with rapid virtual experimentation on a laptop. The ability to comprehensively map out an entire module space across all the critical structures on the device (in a matter of hours or days) is a significant innovation to help be the first to market with a new technology. Last month, Ryan J Patz from Coventor, author of BEOL metallization and patterning whitepapers, gave a very informative and detailed presentation on how Virtual Fabrication is done for BEOL module optimization below the 22nm technology node. The presentation was done live at AVS 60th International Symposium & Exhibition. I was delighted to go through the presentation slides at the Coventor website

The talk provides a procedure for setting up a Virtual Fabrication process flow with automation for process module optimization. Mr. Patz presented example cases of how to use the SEMulator3D platform for identifying unexpected yield detractors, tuning cross-wafer uniformity, optimizing a process module for maximum yield and closed with a proposal to use Virtual Fabrication for feed-forward control to drive down run-to-run variation. Below, I am reproducing some of the key aspects of fabrication discussed in the presentation.

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