As semiconductor technology scales into the 20nm node and beyond, the process complexity, electrical performance and circuit density tradeoff becomes extremely difficult to optimize. As the demand for increased density, lower power, and higher bandwidth accelerates, the motivation for 3D integration becomes more attractive. With the advent of 3D integration comes the promise of “beyond Moore’s law” integration by stacking chip-on-chip and connecting them with through-silicon-vias (TSVs). Numerous definitions of 3D integration exist, for example multi-die packages (also known as system-in-package, or SiP) in which multiple die are mounted on a common substrate that connects them, package-in-package (PiP) where a number of SiPs are mounted in a larger SiP, and package-on-package (PoP) where one SiP is mounted on top of another SiP. All of these approaches offer some degree of density advantage, however, the ultimate objective of 3D integration is the multiple stacking of silicon levels on top of one another, each of which contain subsequent levels of circuitry, all connected with TSVs. This approach to 3D integration has been demonstrated by CEA-Leti and reported in IEEE Spectrum (see Figure 1 below).
While such an approach looks fairly straight forward, the process complexity is quite enormous. Fabricating an entire level of semiconductor circuitry on top of an underlying layer of circuitry is no simple matter. Process temperatures in the top layer devices could adversely affect the characteristics of the bottom layer devices. This potential problem only worsens as additional layers of circuitry are added in future generations. The size of the TSV, usually measured in microns, is also critical since it is significantly larger than the nano-scale dimensions of the underlying silicon devices. This limits the use of TSVs to fairly low-density connections such as those needed to connect logic circuitry to memory cells. Unfortunately, the logic circuit density requirements are much more aggressive than that. Nonetheless, the complexity of “real” 3D integration requires modeling platforms that can accurately model the subtle integration tradeoffs of the process.
Virtual fabrication modeling can work wonders in providing insight into the step-by-step process of a given 3D integration flow. The bottom core-level process can be accurately modeled with the virtual fabrication software platform, while the additional top-level of processing, including the necessary wafer bonding step, can also be modeled. The interaction between the two layers, including interface effects due to the bonding process and the thermal effects that differentiate the two layers, can be systematically studied to ensure the most optimized/defect-free process flow is achieved. The interconnection of the various silicon layers with TSVs is a challenge from an alignment point of view, especially when the TSV connects source/drain diffusions of one level to specific diffusions on the other level. Potential misalignment is a concern, as well as trying to optimize the TSV dimensional constraints with alignment and overlay constraints. This is an area where virtual fabrication can shine. Coventor’s SEMulator3D virtual fabrication platform is a perfect fit for initial process/integration studies for a complicated 3D process flow (see completed 3D virtual fabrication flow below). The platform has the ability to systematically build a complete process flow from starting silicon substrate to final second layer of bonded silicon in a 3D process flow, including the necessary etch steps required to form TSVs. The platform also has the ability to run numerous correlation studies of misalignment and critical dimensional variations to accurately map out the optimal process conditions that result in a completely optimized process flow with a resulting 3D picture of every process step in the flow, from multi-dimensional focal point of viewing. One of the most significant advantages of the SEMulator3D result is the ability to systematically visualize the process flow on a step by step basis to better understand the integration issues, thereby reducing the costly endeavor of running multiple hardware splits to find out.