David Fried, CTO, Coventor, Inc.
It is difficult to imagine what the world of IC design would be like without tools that allow engineers to model, simulate, optimize and “virtually” replicate the millions of gates and transistors that comprise a modern chip. Indeed, it would be literally impossible to design these types of devices without sophisticated automation tools, higher-level abstraction methodologies and extremely accurate simulation, modeling and checking technologies.
To manage ever-increasing complexity, the electronic design automation (EDA) infrastructure has evolved into a highly organized hierarchy. At the lowest level of abstraction, compact models and SPICE serve circuit designers with analytical tools to design small circuits with high precision. At higher levels of abstraction, VHDL, Verilog and synthesis tools allow larger more complex designs to be assembled in virtual space. Routing tools allow massive monolithic products to be wired and analyzed virtually, while essentially ignoring the details of lower levels of this hierarchy. With this advanced EDA infrastructure in place, the design community is now creating massive multi-core processors with embedded memories and advanced I/O capabilities.
While the IC design challenge has been – and continues to be – addressed by automated approaches the question now becomes: what about the underlying physical processes that are meant to be the target for such complex ICs – the manufacturing platforms that are the key to enabling the continuation of Moore’s Law, not to mention opening the door for More than Moore? The development approaches for manufacturing processes as they have rapidly scaled from 90nm to 65nm to 45nm – and are headed for unfathomable 10nm and 7nm nodes – have hardly kept pace with the methods used for the very designs that they are meant to produce.
The situation is compounded by the never-ending battle with device physics, a battle that has given rise to new and sometimes exotic innovations in manufacturing. Recent semiconductor technology advances, including FinFET, TriGate, High-K/Metal- Gate, embedded memories and advanced patterning, all hold tremendous potential to enable scaling and further system-level integration on a single chip. But, they have dramatically increased the complexity of integrated processes as well. The cost and duration of technology development using antiquated trial-and-error experimental methodologies has concurrently increased.