As semiconductor technology scales into the 20nm node and beyond, the process complexity, electrical performance and circuit density tradeoff becomes extremely difficult to optimize. As the demand for increased density, lower power, and higher bandwidth accelerates, the motivation for 3D integration becomes more attractive. With the advent of 3D integration comes the promise of “beyond Moore’s law” integration by stacking chip-on-chip and connecting them with through-silicon-vias (TSVs). Numerous definitions of 3D integration exist, for example multi-die packages (also known as system-in-package, or SiP) in which multiple die are mounted on a common substrate that connects them, package-in-package (PiP) where a number of SiPs are mounted in a larger SiP, and package-on-package (PoP) where one SiP is mounted on top of another SiP. All of these approaches offer some degree of density advantage, however, the ultimate objective of 3D integration is the multiple stacking of silicon levels on top of one another, each of which contain subsequent levels of circuitry, all connected with TSVs. This approach to 3D integration has been demonstrated by CEA-Leti and reported in IEEE Spectrum (see Figure 1 below). read more…
3D printing has become all the rage in many areas, from home hobbyists to high-end industrial applications. The convenience, flexibility, functionality and decreasing price for printing things in 3D makes it an appealing tool for a wide range of purposes. So we thought we’d put it to use for demonstrating how virtual fabrication can help engineers understand the technical nuances of advanced process technologies – as well as show off a cool feature of our SEMulator3D tool. read more…
The recent IEEE Conference on MEMS, held in San Francisco, was one of the better gatherings of its sort, partly due to the location and its proximity to so many participants in the MEMS community, and partly because MEMS is at a real turning point and it is an industry primed for great innovation and advances that can touch all aspects of our lives.
The conference is literally a ‘who’s who’ of the MEMS industry, and not surprisingly there are excellent technical talks on the most important and popular MEMS-related topics such as gyros and accelerometers, optical MEMS, resonators and RF MEMS, energy harvesting and fluidic micro-devices, and biomedical micro-devices. There are tracks covering the complete range of MEMS development – from design, to materials and process characterization, through to fabrication. And there are some pretty advanced, even exotic, topics presented, particularly in the area of health and medical applications.
By David Fried
When I started my semiconductor career, in the midst of quarter-micron CMOS, the work of technology development was very different. We basically knew how to fabricate transistors and interconnects. The structures were pretty well defined, and each generation we embarked on scaling a few key parameters and then resetting the device.
This is not to say that there was a lack of innovation. The industry was undergoing the conversion to copper in the BEOL and some of us to SOI substrates, which represented significant integration, materials and reliability challenges.
But, other than those “big ticket” changes, the processes and integration were stable enough that a large portion of the development effort fell on device engineering. The biggest degrees of process freedom existed in implants and anneals. We spent huge time and resources running and analyzing implant split experiments, clawing out that last 2-3% of drive current and dialing down that last 10-20nA of leakage. As such, TCAD device simulations were absolutely essential. Most process variations were small enough relative to target dimensions to be largely ignored, so TCAD results could directly guide implant and anneal process decisions. read more…
One of the highlight events every year on the MEMS calendar is the IEEE International Conference on MEMS. This is a prestigious gathering that attracts the true thought leaders in MEMS – from both the commercial and academic sides of our industry. The IEEE describes it, quite rightly, as the “flagship annual event of the MEMS community.”
The event organizers often hold the conference in some pretty exotic places – like Cancun, Mexico; Sorrento, Italy; and Istanbul, Turkey. While those are great destinations, it can be hard for some people to justify the travel to their bosses. read more…
by Pawan Fangaria
The design and manufacture of MEMS is very different and in many ways more complex process than even the most advanced ICs. MEMS involve multiple degrees of freedom (i.e. the device to exhibit different characteristics under different physical state, motion or mechanics), making fabrication of MEMS extremely complex; and hence the processes are highly customized and typically linked to particular design or device. The process flow and design parameters are highly sensitive to each other, thus requiring multiple build-and-test cycles and longer MEMS process learning cycles. And these days most of electronic devices or semiconductor designs involve MEMS integrated into them, necessitating a MEMS+IC design approach. For example, gyroscopes are being used in smartphones in big way to enhance motion detection and orientation. Given the cut-throat competition in the mobile market, with increasing feature sets and shrinking windows of opportunity, it’s critical that process learning cycles for MEMS development move from time-consuming build-and-test methods to more efficient methodologies to streamline the handoff from design to manufacturing.
The good news is that Coventor’s SEMulator3D tool (about which I had earlier talked in the context of Virtual Fabrication Platform for semiconductor design ICs) is providing an excellent platform for virtual modeling of MEMS as well. Physical data (such as capacitance) can be extracted from the model for quantitative analysis and process variation studied to quickly predict the exact model of interest before actual fabrication, thus reducing the learning cycle for MEMS.
As always, we are standing by to help you get through any of your end-of-year design needs. Our support personnel are available through the coming week, with the exception of Wednesday December 25 and Wednesday January 1 when our worldwide offices are closed for the holidays.
As a reminder, here is contact information for Coventor resources
System Requirements, Software Downloads, Customer Portal
Email Technical Assistance:
EAST US: email@example.com
WEST US: firstname.lastname@example.org
We look forward to working with you in 2014 to reach new levels of MEMS and IC design success.
I just got back from the annual International Electron Devices Meeting (IEDM) in Washington, DC. As is customary, a great deal of attention was paid to Front End of Line (FEOL) transistor innovations such as FinFET, FDSOI, Graphene, Nanotubes, Nanowires, etc. However, some of the greatest complexity in semiconductor development and manufacturing these days is in the interconnect, or Back End of Line (BEOL). The BEOL contains some of the finest geometries in the technology, since die area scaling is usually limited by the wiring density. Because wires are being designed at such fine dimensions, their height has been increased to recoup the resistance penalty. This makes the dimensions even more challenging through high aspect ratios. Finally, the BEOL contains some of the most complex and unstable materials due to the desire to reduce capacitance (porous low-K dielectrics), the requirement to minimize thermal cycles (for FEOL stability), and the inherent reliability risks associated with the metals involved. I’ve been a transistor specialist for most of my career, but I have to admit… the BEOL has gotten incredibly difficult.