From your friends and partners at Coventor around the world, we wish you best wishes for a safe and happy holiday season, and a prosperous New Year.
As always, we are standing by to help you get through any of your end-of-year design needs. Our support personnel are available through the coming week, with the exception of Wednesday December 25 and Wednesday January 1 when our worldwide offices are closed for the holidays.
As a reminder, here is contact information for Coventor resources
System Requirements, Software Downloads, Customer Portal
Email Technical Assistance:
EAST US: firstname.lastname@example.org
WEST US: email@example.com
We look forward to working with you in 2014 to reach new levels of MEMS and IC design success.
I just got back from the annual International Electron Devices Meeting (IEDM) in Washington, DC. As is customary, a great deal of attention was paid to Front End of Line (FEOL) transistor innovations such as FinFET, FDSOI, Graphene, Nanotubes, Nanowires, etc. However, some of the greatest complexity in semiconductor development and manufacturing these days is in the interconnect, or Back End of Line (BEOL). The BEOL contains some of the finest geometries in the technology, since die area scaling is usually limited by the wiring density. Because wires are being designed at such fine dimensions, their height has been increased to recoup the resistance penalty. This makes the dimensions even more challenging through high aspect ratios. Finally, the BEOL contains some of the most complex and unstable materials due to the desire to reduce capacitance (porous low-K dielectrics), the requirement to minimize thermal cycles (for FEOL stability), and the inherent reliability risks associated with the metals involved. I’ve been a transistor specialist for most of my career, but I have to admit… the BEOL has gotten incredibly difficult.
At the 2013 edition of the IEDM conference held this month in Washington, DC, some of the brightest minds in the design and manufacture of semiconductors gathered to discuss trends and challenges in the IC industry. One particular session, hosted by Coventor, assembled 5 experts on leading edge process development from some of the biggest chip players in the business: IBM, GlobalFoundries, Samsung, ST Microelectronics and renowned research organization IMEC.
Coventor CTO David Fried leads a panel of industry experts on a discussion of how to address challenges to continued IC scaling
The consensus of this elite group was not surprising: there is no shortage of new and unprecedented challenges standing in the way of continued scaling of IC technology. Each panelist offered their own opinion on what the biggest challenge is, and they ran the gamut of tough tasks.
By Richard Goering on December 11, 2013
Micro-electrical mechanical systems (MEMS) have been a niche technology for many years, but a new generation of MEMS ICs is emerging, according to Mike Jamiolkowski, CEO of Cadence partner and MEMS tool provider Coventor. Barriers to the use of MEMS technology, such as the need for PhD-level experts and non-reusable foundry processes, are starting to ease.
In this interview Jamiolkowski talks about new trends in the MEMS market, discusses his company’s MEMS+ tools and how they work with the Cadence Virtuoso platform, and notes a new MEMS+ capability to output reduced order models in the Verilog-A language.
Posted by: Gerold Schröpfer, Director of European Operations and Foundry Partner Program
Without MEMS today’s smart phones wouldn’t be called “smart”. Be it motion sensing with accelerometers and gyroscopes, noise cancelling with multiple microphones, multi-band radios with tunable RF MEMS capacitors, MEMS are one of the key enablers for completely new or substantially improved functionaloties. This is true not only for smart phones but for many other intelligent devices, in many different application domains. In Europe, we call them “Smart Systems”.
While smart phones and smart systems are becoming coming common place, current industry practices for designing these complex systems are not so smart. According to Salvatore Rinaudo, Industrial and Multi-Segment Sector CAD R&D Director at STMicroelectronics, the lack of a structured design methodology is ‘…the major obstacle to the rapid expansion of smart systems applications.’ Smart system developers use separate design tools for different parts of the system, and most of them do not take the overall system integration into account. Rinaudo made this statement in 2011, but it’s just as relevant today. To address this challenge, key European stake holders have joined forces in two collaborative R&D consortia. One of them is SMAC, which stands for ‘SMArt systems Co-design’, combining expertise from smart systems manufacturers, EDA vendors and academic institutions under the leadership of ST. The other is PARSIMO and focuses on partitioning and modeling of Systems in Package (SIP). read more…
By David Fried
Tech Design Forum
Will we be able to engineer another technology node that brings the usual cost and area savings without EUV lithography? I have serious doubts.
EUV lithography was supposed to be ready for the 45nm process node, and was then delayed until 32nm and later, 22nm. Today, major semiconductor companies are continuing to develop their offerings. Some will use the upcoming IEDM to detail their 1xnm processes, developed despite the lack of EUV’s patterning capabilities.
Why the delay with EUV? The story has been told many times: a combination of complex electro-optics, problems with the power of the illumination source, resist sensitivity and defectivity. The list of EUV challenges is long, but the summary is short: it’s not ready yet!
by Pawan Fangaria
The growing process integration complexity at each technology node has increased development time and cost, and this trend looks to continue. There is a looming risk of delivering unrepeatable critical unit processes (or process modules) that would require revisiting development and manufacturing requalification or in severe cases a design re-spin. Below the 22nm process node, tremendous effort is necessary to meet process integration specifications with a yielding process that is robust in the face of unavoidable manufacturing variation. read more…
By Steve Breit, V.P. Engineering
MEMS sensors never stand on their own – there’s always an accompanying ASIC that conditions the MEMS output or controls the MEMS. We’ve written frequently in past blogs and white papers about the barrier between MEMS and ASIC design teams. For purposes of functional verification, the ASIC designers need a MEMS block on their schematics, with an underlying model that captures the behavior of the MEMS. The problem arises because the MEMS and ASIC design teams use fundamentally different approaches to simulate the functioning of their respective designs. The MEMS designers use finite element analysis tools while the ASIC designers use analog/mixed-signal circuit simulators such as Cadence Spectre. There’s simply no way to include a conventional finite element model in a circuit simulator, and even if there was the simulations would run so slowly that it would have no practical use. To overcome this incompatibility, all MEMS companies that we’ve engaged with rely on handcrafting models of their MEMS devices in a hardware description language like Verilog-A that is compatible with the ASIC team’s circuit simulator. It takes lots of time, specialized knowledge, and skills to handcraft and verify a MEMS device model in Verilog-A. Because of the technical difficulty, handcrafted models are typically overly simplified, omitting important aspects of the MEMS behavior such as cross coupling between mechanical modes and non-linear effects. Moreover, an ongoing effort is needed to keep the handcrafted models in sync with the actual MEMS design, leaving plenty of opportunities for version skew and human error. The end result, undoubtedly, is extra design spins that are costly not only in engineering time, but in longer time to market. The graphic below illustrates this barrier.