Coventor Blog

Rapid Yield Optimization at 22nm Through Virtual Fab
by Pawan Fangaria

Remember? During DAC 2013 I talked about a new kind of innovation: A Virtual Fabrication Platform, SEMulator3D, developed by COVENTOR. Now, to my pleasant surprise, there is something to report on the proven results from this platform. IBM, in association with COVENTOR, has successfully implemented a 3D Virtual Fabrication methodology to rapidly improve the yield of high performance 22nm SOI CMOS technology.

The CTO-Semiconductor of COVENTOR, Dr. David M. Fried was in attendance while IBM’s Ben Cipriany presented an interesting paper on this work at The International Conference on Simulation of Semiconductor Processes and Devices (SISPAD 2013). The paper is available at the link “IBM, Coventor present 22nm Virtual Fabrication Success at SISPAD” at the COVENTOR website.

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IBM, Coventor present 22nm virtual fabrication success at SISPAD

GLASGOW, Scotland – September 4, 2013 – IBM and Coventor jointly presented a paper at the 2013 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD). The paper presents a technology development methodology that relies on 3D virtual fabrication using Coventor’s SEMulator 3D platform to rapidly improve yield by increasing tolerance to multilevel process variation. This methodology has been successfully implemented in the development and yield ramp of high–performance 22nm SOI CMOS technology. Based on virtual metrology, dedicated test site structures were designed and implemented, with electrical results corroborating virtual findings, validating the methodology. This 3D virtual fabrication technique was used to implement a delicate process change, and the same test site structures validated the improved process window yield. read more…

Coventor’s SEMulator3D 2013 Addresses New Requirements of 3D Fab Era With Process Modeling Accuracy and Automation Breakthroughs

Latest release of the industry’s only ‘virtual fabrication’ platform delivers advanced physics-driven predictive modeling capabilities aimed at reducing silicon learning cycles and costs

CARY, North Carolina – May 28, 2013 – Coventor®, Inc., the leading supplier of virtual fabrication solutions for semiconductor devices and micro-electromechanical systems (MEMS), today announced immediate availability of the SEMulator3D® 2013 software platform. SEMulator3D 2013 brings unprecedented physical accuracy and predictive modeling capabilities to process development and integration. This milestone release expands the value of ‘virtual fabrication’ to the broader semiconductor ecosystem in order to dramatically reduce silicon learning cycles and the billions of dollars spent reaching manufacturing readiness. read more…

Coventor provides a chapter for latest book on MEMS design: System-level Modeling of MEMS.

A new and very comprehensive book on MEMS design is now available, and we are proud to point out that a couple of Coventor MEMS experts have provided the first chapter.

This practical handbook fills a gap in the literature available on advanced micro and nanosystems. It addresses the three most important approaches of system-level modeling:
1) physical modeling with lumped elements and Kirchhoffian networks, 2) modal modeling to accurately describe the mechanical domain, and 3) mathematical modeling employing, for example, model-order reduction methods.

Editors and authors from industry and research discuss the physical and mathematical underpinnings and methods of MEMS modeling in a clearly understandable and sufficiently detailed manner. Tailored to practitioners and engineers, authors present the advantages and pitfalls of each method — and how to avoid the latter – so readers can choose the method most suitable for their specific application requirements.
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Virtual Fabrication Allows Process Development to Keep Pace

GSA Forum
David Fried, CTO, Coventor, Inc.

It is difficult to imagine what the world of IC design would be like without tools that allow engineers to model, simulate, optimize and “virtually” replicate the millions of gates and transistors that comprise a modern chip. Indeed, it would be literally impossible to design these types of devices without sophisticated automation tools, higher-level abstraction methodologies and extremely accurate simulation, modeling and checking technologies.

To manage ever-increasing complexity, the electronic design automation (EDA) infrastructure has evolved into a highly organized hierarchy. At the lowest level of abstraction, compact models and SPICE serve circuit designers with analytical tools to design small circuits with high precision. At higher levels of abstraction, VHDL, Verilog and synthesis tools allow larger more complex designs to be assembled in virtual space. Routing tools allow massive monolithic products to be wired and analyzed virtually, while essentially ignoring the details of lower levels of this hierarchy. With this advanced EDA infrastructure in place, the design community is now creating massive multi-core processors with embedded memories and advanced I/O capabilities.

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Coventor Ships Latest Version of MEMS+IC Co-Design Platform to Accelerate Development of Complex 3D Electronics Systems

MEMS+ 3.0 software platform delivers new fluidic, package and noise simulation capabilities; an expanded component library; and performance enhancements

CARY, North Carolina – February 4, 2013 – Coventor®, Inc., the leading supplier of design automation software for developing micro-electromechanical systems (MEMS), today announced immediate availability of its new MEMS+® 3.0 design platform that accelerates development of complex 3D systems with state-of-the-art actuators, accelerometers and gyroscopes, microphones and other types of MEMS devices.
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