Press Coverage

IMEC Technology Forum at SEMICON – Coventor could save you billions!

semiwiki-logoBy Scotten Jones

The development of leading edge semiconductor technology is incredibly expensive, with estimates ranging from a few to several billion dollars for new nodes. The time to develop a leading edge process is also a critical competitive issue with some of the largest opportunities awarded based on who is first to yield on a new node.

Being late to market can cost a semiconductor company billions of dollars in lost opportunities! Coventor produces SEMulator3D, a modeling platform that enables development engineers to simulate process flows in full 3D to test and refine them before running wafers, reducing development costs and speeding up time to market. David Fried is the CTO of Coventor and he presented at the IMEC Technology Forum (ITF) on Monday before SEMICON. I was at David’s presentation and I also had the opportunity to interview him on Wednesday during the show.

read the full article here.


Industry Award for Coventor

Silicon Semiconductor Logo Coventor, Inc., supplier of automated software solutions for semiconductor devices and micro-electromechanical systems (MEMS), has announced its SEMulator3D 6.0 won the 2016 “Best of the West” award sponsored by Solid State Technology and SEMI at SEMICON West. This industry award recognizes the product and technology developments that contributed the most significant improvements to the electronics manufacturing supply chain. Coventor’s SEMulator3D was selected for the significant financial, scientific and social impact it has had on the industry.

Coventor’s SEMulator3D is a 3D virtual fabrication platform that predictively models how next-generation processes including FinFETs, 3D NAND Flash, BEOL, Nanowires, 3D-IC, FDSOI, and DRAM will perform in the fab. Combining design data with advanced physics and deep process knowledge, SEMulator3D creates a “virtual” silicon wafer and mimics a series of unit processes like those in the fab resulting in highly-accurate 3D computer models of the predicted structures on wafer.

read the full article here.

Coventor wins “Best of West” Award

logoBy Pete Singer, Editor-in-Chief

On Wednesday, Solid State Technology and SEMI announced the recipient of the 2016 “Best of West” Award — Coventor — for its SEMulator3D. The award recognizes important product and technology developments in the electronics manufacturing supply chain. The Best of West finalists were selected based on their financial impact on the industry, engineering or scientific achievement, and/or societal impact.

read the full article here.

When Galaxies Collide – Synopsys TCAD and Coventor Start to Overlap


By Bryon Moyer

Astronomy bestows lavish breathless anticipation upon one of the great events of the universe: two galaxies running into (or through) each other. The thing is, it happens breathtakingly slowly – each stately galaxy spinning away, the distance between them slowly evaporating. Watching it is something of a sampling exercise: see where they are; nap for a couple of centuries. Wake, see that, yup, they’re a little closer; nap. Wake again, grab a new beer, and doggonnit if they aren’t just a wee bit closer yet. Basketball it’s not.

Well, we may have something of a similar event in play in EDA-land. Although referring simply to two galaxies isn’t quite fair: one, Synopsys, is perhaps more of a galaxy cluster to Coventor’s galaxy. To set the scene, let’s examine the status quo – the gap between the companies – and then we’ll look at each one to see how that gap is closing. And we’ll hopefully do it in a way that doesn’t involve napping.

read the full article here.

Are We There Yet? The Road to 7nm is Paved with Predictive Modeling

 By Amelia Dalton

Sometimes the road less traveled is less traveled for a reason. (Jerry Seinfeld)

We know what roads will lead us to the 7nm semiconductor node and frankly, they’re not all that scenic. In this week’s Fry Fry, we tackle the trials and tribulations of this tiny titan with David Freid from Coventor. David and I discuss the biggest challenges we will face at this smallest of the small process geometry, how virtual fabrication and predictive modeling can help solve some of our problems, and why the most important question surrounding this new node isn’t being asked: “Should we even go to 7nm?”

Listen to the podcast here.

Brainstorm: Wearables

ProductDesignDevelopment By PD&D Staff, Product Design and Development

In the Product Design & Development Brainstorm, we talk with industry leaders to get their perspective on issues critical to the design engineering marketplace.

In this issue, we ask: What are some of the key technology trends that will shape the evolution of the wearables market?

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RC extraction from ‘virtual fab’ models may speed PDK availability

Tech Design Forum Logo By Luke Collins, Tech Design Forum

Coventor has updated its SEMulator3D virtual fabrication tool so it can extract predicted resistance and capacitance values from its models. The analysis tool could be used to speed up the availability of early PDKs for rapidly evolving processes.

SEMulator3D abstracts IC manufacturing steps into behavioural models, so that it can simulate a a whole process in a ‘virtual fab’. Because the process steps are modeled using behavioural abstractions, rather than full physics, it becomes practical to run multiple options to explore how variations in each step will affect overall outcomes.

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DAC: Coventor Adds Electrical Analytics to SEMulator3D Version 6.0

ee-timesBy R. Colin Johnson, EE Times

LAKE WALES, Fla.—What began as a microelectromechanical systems (MEMS) 3-D design tool has transformed into a 3-D semiconductor design tool which has accordingly added Electrical Analytics to the latest version six of Coventor’s SEMulator3D. See Coventor’s SEMulator3D at the Design Automation Conference (DAC 2016, Austin, Texas, June 5-9), booth 321.

Besides chip designers—now its biggest user segment—are systems designers who, the company claims, make up its fastest growing customer segment. System designers are most interested in how process variations impact their product’s yield robustness, according to David Fried, chief technology officer (CTO) of semiconductors for Coventor.

read the full article here