by Paul McLellan
The last paradigm shift in DRC was around 0.35um when designs got too large to handle as flat data, and hierarchical approaches were required. Back then the design rules themselves were not that complex, the explosion of data volume came from the complexity of the design itself. But each process node added more design rules intricacies and many new types of rules that needed to be checked.
by Tom Simon
Recently I attended a panel discussion on variability in semiconductor fabrication hosted by Coventor in conjunction with the IEEE IEDM conference in San Francisco. The IEEE bills the conference as “the world’s pre-eminent forum for reporting technological breakthroughs in the areas of semiconductor and electronic device technology, design, manufacturing, physics, and modeling.” It’s easy to see how this discussion was relevant to the conference focus. SemiWiki’s own Dan Nenni was the panel moderator.
by Paul McLellan
IEDM (technically the International Electron Devices Meeting although I’ve never heard anyone use the full name) is in a couple of weeks time, in San Francisco. It is December 15-17th at the Hilton Union Square (which is not actually at Union Square but nearby at 333 O’Farrell Street).
For the last few years on the Tuesday evening Coventor have sponsored an event (with appetizers and drinks). Last year it was all about collaboration. This year the topic is variation, Survivor, Variation in the 3D Era. It is at the Hotel Nikko from 5.30pm to 8.30pm on Tuesday December 16th in the Carmel Room. Hotel Nikko is 222 Mason Street just around the corner from the Hilton.
Imec researchers using Coventor’s SEMulator3D platform to model and optimize 7nm manufacturing technology
LEUVEN, BELGIUM – Belgian nanoelectronics research center imec has announced a joint development project with Coventor, a leading supplier of semiconductor process development tools. The collaboration will enable faster and more optimized development of advanced manufacturing technology in the 3D device architecture era, extending down to imec’s 10- and 7-nanometer (nm) processes.
Coventor SEMulator3DImec and Coventor, the process development tool vendor, are to co-develop 10nm and 7nm 3D CMOS processes. To adopt the 7nm node, the industry needs to select the optimal layout, as well as optimise process step performance and control methodology. Using Coventor’s SEMulator3D platform, engineers from Imec and Coventor are working together to reduce silicon learning cycles and development costs by down selecting the options for development of next-generation manufacturing technologies.
Today imec and Coventor announced a joint development project for 10nm and 7nm process development. Imec, which is in Leuven Belgium, is a partner with pretty much all the semiconductor companies that are planning work at these advanced nodes. It mostly does pre-competitive research and development. This type of research is very expensive for any one semiconductor company to carry out so it makes sense to share the investment across the entire industry. It will be interesting to see whether the GlobalFoundries acquisition of IBM’s semiconductor business changes the landscape since historically IBM has done a lot of research themselves, and those researchers now work for GF. Imec is a big operation with a staff of over 2000 people, including 670 industrial residents and guest researchers.