Press Coverage

Coventor and Imec link on virtual fabrication

By Dave Manners

Coventor, the supplier of virtual fabrication technology for ICs and MEMS, has worked with a team from Imec to compare the effects of variability on different semiconductor fabrication processes.

Coventor and its customers use virtual fabrication to deepen the understanding of what’s required to incorporate new lithography technologies.

Coventor has conducted a series of studies aimed at understanding semiconductor lithography and manufacturing issues that could affect yield and device density at future technology nodes (N7 and lower).

read the full article here.

New Embedded Memories Ahead

By Mark Lapedus

The embedded memory market is beginning to heat up, fueled by a new wave of microcontrollers (MCUs) and related chips that will likely require new and more capable nonvolatile memory types.

The industry is moving on several different fronts in the embedded memory landscape. On one front, traditional solutions are advancing. On another front, several vendors are positioning the next-generation memory types, such as FRAM, MRAM, ReRAM and even carbon nanotube RAMs, for the embedded market.

read the full article here.

Transferring Skills Getting Harder

By Ed Sperling

Rising complexity in developing chips at advanced nodes, and an almost perpetual barrage of new engineering challenges at each new node, are making it more difficult for everyone involved to maintain consistent skill levels across a growing number of interrelated technologies.

The result is that engineers are being forced to specialize, but when they work with other engineers with different specialties they frequently don’t understand where the gaps are. Not everyone is speaking the same language—sometimes literally—and the skills at one process node may be markedly different from another. That allows errors to creep in at every level, increasing the number of re-spins and overall costs, decreasing yield, and stretching out time to market.

read the full article here.

EDA in the year 2017 – Part 1

By Gabe Moretti

The EDA industry performance is dependent on two other major economies: one technological and one financial.  EDA provides the tools and methods that leverage the growth of the semiconductor industry and begins to receive its financial rewards generally a couple of year after the introduction of the new product on the market.  It takes that long for the product to prove itself on the market and achieve general distribution.

David Fried from Coventor addressed the most important topics that may impact the foundry business in 2017.  He made two points.

read the full article here.

MEMS and ASIC Design: How the Gap Can Narrow

By Anne Fisher

As the MEMS ecosystem matures, what role will foundries play in its success?

The occasion of the 2016 MEMS Executive Congress made for a good opportunity to meet with Dr. Stephen R. Breit, VP Engineering at Coventor, a MEMS design automation firm. Breit prefaced our interview by noting his company’s concern with, and work toward, overcoming the ASIC design/MEMS design divide. “We were ahead of the industry in that we have been focused for years on bridging that gap,” Breit told EECatalog, “but the industry is now catching up with us and realizing that gap exists.” Breit also spoke about foundries’ motivations vis-à-vis MEMS, the elements found in a successful design kit, and which decisions support More than Moore—among other topics. Edited excerpts of the interview follow.

 

read the full article here.

BEOL Issues At 10nm And 7nm

By Ed Sperling

Semiconductor Engineering sat down to discuss problems with the back end of line at leading-edge nodes with Craig Child, senior manager and deputy director for GlobalFoundries’ advanced technology development integration unit; Paul Besser, senior technology director at Lam Research; David Fried, CTO at Coventor; Chih Chien Liu, deputy division director for UMC’s advanced technology development Module Division; and Anton deVilliers, director of patterning technology and senior member of the technical staff at Tokyo Electron. What follows are excerpts of that conversation.

Experts at the table, part 1: Lines blur with middle of line as RC delay increases, reliability and yield become more difficult to achieve, and costs skyrocket.

Experts at the table, part 2: The impact and cost of air gap; reducing RC delay with liner-less approaches and cobalt; where EUV will make a dent…maybe.

Experts at the table, part 3: EUV, metallization, self-alignment, ALD, and the limits of copper.

IEDM: Coventor Panel on BEOL Challenges

By Paul McLellan

At the recent IEDM in San Francisco, Coventor organized a panel titled BEOL Barricades: Navigating Future Semiconductor Yield, Reliability, and Cost Challenges. The BEOL, back end of line, is the metal, although where it begins and ends, as you will see, is debatable.

The panel was moderated by Ed Sperling and the panelists were:

  • Paul Besser of LAM Research
  • Chih-Chien Liu of UMC
  • Craig Child of GLOBALFOUNDRIES
  • Anton deVilliers of Tokyo Electron
  • David Fried of Coventor

 

read the full article here.

Uncertainty Grows For 5nm, 3nm

By Mark Lapedus

As several chipmakers ramp up their 10nm finFET processes, with 7nm just around the corner, R&D has begun for 5nm and beyond. In fact, some are already moving full speed ahead in the arena.

TSMC recently announced plans to build a new fab in Taiwan at a cost of $15.7 billion. The proposed fab is targeted to manufacture TSMC’s 5nm and 3nm processes, which are due out in 2020 and 2022, respectively. Other chipmakers, including GlobalFoundries, Intel and Samsung, also are looking at technologies for 5nm and beyond.

read the full article here.