Press Coverage

MEMS: A Tale Of Two Tough Markets

By Ed Sperling

The MEMS market is growing rapidly, profits not so much.

In most market segments, this would be a signal that more automation and standardization are required. But in the microelectromechanical systems world, fixes aren’t so simple. And even where something can be automated, that automation doesn’t work all the time. In fact, while MEMS devices are extremely difficult to design, build and manufacture, the business side of the market is arguably even tougher to manage.

MEMS devices are created through a combination of electrical and mechanical engineering. Included in this category are inertial sensors, such as gyroscopes and accelerometers, both of which are present in almost every mobile device to detect motion. The combination of MEMS devices is how Google’s Waze, a popular peer-to-peer GPS application, can tell if you’re stuck in traffic or moving, how fast you’re moving, and when you’re likely to arrive at your destination given current traffic conditions. There also are compasses, vibration sensors, as well as capacitive touch sensors for security.

read the full article here.

Battling Fab Cycle Times

By Mark LaPedus

The shift from planar devices to finFETs enables chipmakers to scale their processes and devices from 16nm/14nm and beyond, but the industry faces several challenges at each node.

Cost and technical issues are the obvious challenges. In addition, cycle time—a key but less publicized part of the chip-scaling equation—also is increasing at every turn, creating more angst for chipmakers and customers alike. In fact, cost, technical hurdles and cycle time are all contributing to the ongoing slowdown of Moore’s Law.

Cycle time is the amount of time it takes to process a wafer lot in a fab from start to finish. Typically, a wafer lot consists of 25 wafers, which move through various process steps in a fab. An advanced logic process could have from 600 to 1,000 steps or more.

A simple way to look at cycle time is to apply a probability theory called Little’s Law in the fab. In this case, cycle time equals work-in-process (WIP) over the start rate, according to KLA-Tencor. For example, if a fab has 12,000 lots, and it processes 4,000 lots per month, the total cycle time is 3 months, according to KLA-Tencor.

read the full article here.

Coventor and Imec link on virtual fabrication

By Dave Manners

Coventor, the supplier of virtual fabrication technology for ICs and MEMS, has worked with a team from Imec to compare the effects of variability on different semiconductor fabrication processes.

Coventor and its customers use virtual fabrication to deepen the understanding of what’s required to incorporate new lithography technologies.

Coventor has conducted a series of studies aimed at understanding semiconductor lithography and manufacturing issues that could affect yield and device density at future technology nodes (N7 and lower).

read the full article here.

New Embedded Memories Ahead

By Mark Lapedus

The embedded memory market is beginning to heat up, fueled by a new wave of microcontrollers (MCUs) and related chips that will likely require new and more capable nonvolatile memory types.

The industry is moving on several different fronts in the embedded memory landscape. On one front, traditional solutions are advancing. On another front, several vendors are positioning the next-generation memory types, such as FRAM, MRAM, ReRAM and even carbon nanotube RAMs, for the embedded market.

read the full article here.

Transferring Skills Getting Harder

By Ed Sperling

Rising complexity in developing chips at advanced nodes, and an almost perpetual barrage of new engineering challenges at each new node, are making it more difficult for everyone involved to maintain consistent skill levels across a growing number of interrelated technologies.

The result is that engineers are being forced to specialize, but when they work with other engineers with different specialties they frequently don’t understand where the gaps are. Not everyone is speaking the same language—sometimes literally—and the skills at one process node may be markedly different from another. That allows errors to creep in at every level, increasing the number of re-spins and overall costs, decreasing yield, and stretching out time to market.

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EDA in the year 2017 – Part 1

By Gabe Moretti

The EDA industry performance is dependent on two other major economies: one technological and one financial.  EDA provides the tools and methods that leverage the growth of the semiconductor industry and begins to receive its financial rewards generally a couple of year after the introduction of the new product on the market.  It takes that long for the product to prove itself on the market and achieve general distribution.

David Fried from Coventor addressed the most important topics that may impact the foundry business in 2017.  He made two points.

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MEMS and ASIC Design: How the Gap Can Narrow

By Anne Fisher

As the MEMS ecosystem matures, what role will foundries play in its success?

The occasion of the 2016 MEMS Executive Congress made for a good opportunity to meet with Dr. Stephen R. Breit, VP Engineering at Coventor, a MEMS design automation firm. Breit prefaced our interview by noting his company’s concern with, and work toward, overcoming the ASIC design/MEMS design divide. “We were ahead of the industry in that we have been focused for years on bridging that gap,” Breit told EECatalog, “but the industry is now catching up with us and realizing that gap exists.” Breit also spoke about foundries’ motivations vis-à-vis MEMS, the elements found in a successful design kit, and which decisions support More than Moore—among other topics. Edited excerpts of the interview follow.

 

read the full article here.

BEOL Issues At 10nm And 7nm

By Ed Sperling

Semiconductor Engineering sat down to discuss problems with the back end of line at leading-edge nodes with Craig Child, senior manager and deputy director for GlobalFoundries’ advanced technology development integration unit; Paul Besser, senior technology director at Lam Research; David Fried, CTO at Coventor; Chih Chien Liu, deputy division director for UMC’s advanced technology development Module Division; and Anton deVilliers, director of patterning technology and senior member of the technical staff at Tokyo Electron. What follows are excerpts of that conversation.

Experts at the table, part 1: Lines blur with middle of line as RC delay increases, reliability and yield become more difficult to achieve, and costs skyrocket.

Experts at the table, part 2: The impact and cost of air gap; reducing RC delay with liner-less approaches and cobalt; where EUV will make a dent…maybe.

Experts at the table, part 3: EUV, metallization, self-alignment, ALD, and the limits of copper.