Achieving high yields with acceptable costs is becoming much more difficult as chipmakers migrate to next-generation 3D NAND and finFET devices—but not just because of rising complexity or lithography issues.
To fabricate an advanced logic chip, for example, a wafer moves from one piece of equipment to another in what amounts to 1,000 process steps or more in a fab. Any glitch with the equipment or a process step can cause defects, thereby impacting yield. The culprit may be a malfunction in seemingly insignificant parts or sub-systems in the equipment itself.
Posted in: Press Coverage by Sandra Liu | Comments Off on From Movies to Data Analysis – Coventor’s SEMulator 3D PivotsThursday, August 17, 2017
By Bryon Moyer
If you’ve been paying attention to the various papers at various advanced semiconductor process conferences, there’s a name you’re seeing more and more: Coventor. We’ve looked at them several times before, in the context of both their SEMulator 3D tool and their MEMS+ tool – the former for development of new semiconductor processes and the latter for designing MEMS devices.
Today we’re focusing on the SEMulator 3D tool, whose 6.1 version was recently announced. We’re doing so because the tool has turned a corner on how it’s used. Before going there, let’s talk about where we’ve been first in order to set the stage.
Chipmakers are readying their next-generation technologies based on 10nm and/or 7nm finFETs, but it’s still not clear how long the finFET will last, how long the 10nm and 7nm nodes for high-end devices will be extended, and what comes next.
The industry faces a multitude of uncertainties and challenges at 5nm, 3nm and beyond. Even today, traditional chip scaling continues to slow as process complexities and costs escalate at each node. As a result, fewer customers can afford to design chips around advanced nodes.
Posted in: Press Coverage by Sandra Liu | Comments Off on “Problems and Solutions at 7nm” – David Fried Video Interview with Semiconductor EngineeringMonday, July 24, 2017
David Fried, Chief Technology Officer of Coventor, has a discussion with Ed Sperling of Semiconductor Engineering about what’s going on at 7nm, and some of the problems that we’re starting to experience at both 7nm and 5nm.
Posted in: Press Coverage by Sandra Liu | Comments Off on Scaling the Analytic Mountains – How Big Data is Changing the Course of the Semiconductor IndustryFriday, July 14, 2017
By Amelia Dalton
It’s coming. He knows it is. It’s only a matter of time before it buries him. His story is not unique. It’s been played out in our industry over and over again. He’s suffering from BUAMODS – or – Buried Under A Mountain Of Data Syndrome. But what’s the cure for this ailment? How do we dig ourselves out from underneath this mountain of analytics? In this week’s episode of Fish Fry, we strike at the very heart of this issue. Dr David Fried (CTO – Coventor) joins us to discuss how big analytics are changing the course of the semiconductor industry. We talk about the value of process variant experiments and how process modeling will affect the future of advanced 3-D technologies. Also this week, we check out a new 3-D prototype chip from MIT and Stanford University that combines data storage and computing in a single chip with a little help from multiple nanotechnologies.
While chipmakers are keen to move to the 7nm node, the use of ‘tricks’ to extend the life of optical lithography, amidst a continuing wait for EUV, is piling up the design challenges.
“In the last five to six years, we have gone through six to seven nodes, starting with variants of 28nm,” said Balaji Velikandanathan, quality engineer at Qualcomm, in a panel session at June’s Design Automation Conference. “We are talking about [moving from] inception to tapeout in nine months and [introducing] a new process node every year.”
Qualcomm wants to move to 7nm to push frequency to 3GHz and reduce power by 30%, compared to the 10nm Snapdragon 835 used in phones such as the HTC U11.
Posted in: Press Coverage by Sandra Liu | Comments Off on Coventor Announces SEMulator3D 6.1 and New Analytics CapabilitiesWednesday, July 5, 2017
Coventor Announces SEMulator3D 6.1 and New Analytics Capabilities
Coventor’s Virtual Fabrication Platform Provides Statistical Insight into Process Variation Challenges
CARY, NC– June 22, 2016 – Coventor®, Inc., the leading supplier of automated software solutions for semiconductor devices and micro-electromechanical systems (MEMS), today announced the availability of SEMulator3D® 6.1 – the latest version of its semiconductor virtual fabrication platform. This new version further increases the accuracy of the process simulation, geometry and modeling of advanced semiconductor processes with new features and usability enhancements. Along with SEMulator3D Version 6.1, Coventor is releasing an all-new SEMulator3D Analytics add-on component that automates statistical analysis of process variation directly from within the SEMulator3D process-predictive platform.
The value of the internet of things lies in the data generated by billions of connected devices, and those devices need sensors to generate that data. Sensors measure temperature, light, speed, position, moisture, flow rate, activity level … almost anything you can measure with your five senses and some things you can’t even perceive.
Sensors are often paired with actuators, miniature machines that perform a function based on digital instructions. For example, a sensor could measure how quickly liquid flows through a pipe, and an actuator could trigger a valve to stop the flow.