IMEC, Coventor model 10nm, 7nm processesEuropean research institute IMEC (Leuven, Belgium) has announced a joint development project with EDA tools vendor Coventor Inc. (Cary, North Carolina) to work on the modeling of next-generation manufacturing processes using Coventor’s SEMulator 3D software.
by Paul McLellan, SemiWiki
One of the things about MEMS devices is that they almost always live on a chip that also contains the electronics necessary to process the output from the sensor. For example, an on-chip accelerometer for a car airbag deployment will contain the electronics necessary to process the signal from the sensor and end up with something much closer to “we’re crashing, deploy the airbags” versus “we’re OK, don’t fire off the airbags.”
The design of the MEMS devices themselves are typically done with some form of finite-element analysis (FEA), a very general approach to designing mechanical structures. However, these models of the device are very complex and slow to evaluate due to the huge number of degrees of freedom. This is fine for designing the device itself but for working with the electronics a simpler model of the device is required that is accurate enough for the purpose but is also fast to evaluate.
By Francoise von Trapp
3D In-Depth, EDA Tools
I don’t usually write about MEMS. But every once in a while, when MEMS (stands for micro-electromechanical systems) touches anything to do with 3D integration, usually at the system-level, I might veer slightly out of my comfort zone to interview a MEMS supplier about their latest developments. I find it’s a good way to learn about the synergies and to cross-pollinate information. Today was one of those days. I interviewed Steve Breit, PhD, VP of Engineering, Coventor, supplier of design automation software for MEMS and semiconductor applications. Breit reminded me that through silicon via technology (TSV), which is critical for 3D IC, owes a debt to MEMS. He’s right about that. So I figure a nod to MEMS now and again on 3D InCites isn’t out of place.
Breit briefed me on the company’s latest version of its MEMS+ modeling environment for accelerated development of advanced MEMS devices and systems, and what the improvements mean for ASIC designers who need to integrate MEMS devices into their system design.
by Paul McLellan
At SEMICON last month, Rohit Pal of GlobalFoundries gave a presentation on their methodology for reducing process variation. It was titled Cpk Based Variation Reduction: 14nm FinFET Technology.
Capability indices such as Cpk is a commonly used technique to assess the variation maturity of a technology. It looks at a given parameter’s variability and compares it to 6 sigma. The higher the number the better, 1.33 should have the process yielding close to 100% (for that parameter) and 2 is the full 6 sigma. Using Cpk makes it easy to track metrics to assess variation improvement for a technology. They can also be used as a gating item for technology milestone achievement. However, it is not truly an absolute value, it is a function of the specification limits.
by Pawan Fangaria
We all know that Technology Computer Aided Design (TCAD) simulations are essential in developing processes for semiconductor manufacturing. From the very nature of these simulations (involving physical structure and corresponding electrical characteristics of a transistor or device), they are predominantly finite-element based simulations with complex set of equations to be solved which require large computation, thus increasing simulation time exponentially with the size of the device. It was okay for earlier generations of semiconductor technology nodes to rely on transistor or small cell level process and characterization to develop large designs which were then verified through several build-and-test cycles through actual foundries. However, for today’s nanometer technology nodes and large, complex, high-density designs with complex transistor structures like FinFET and others which exhibit excessive variability in manufacturing, it’s clear that the same old methodology will no longer be effective. . Along with the technology, the economics of chip manufacturing and marketing has become equally pressing, needing substantial reduction in P/Q ratio and very high TAT in order take advantage of ever shrinking windows of opportunity.
by Paul McLellan
One of Coventor’s flagship products is SEMulator3D, and at Semicon West they announced a new version, 2014.100.
SEMulator3D is a powerful 3D semiconductor and MEMS process modeling platform. It uses highly efficient physics-driven voxel modeling technology. It models the physical effects of process steps, which is where all the current challenges are.
Combining the two-dimensional design layout with the process description gives it the capability to model the process flows and determine what will be manufactured with that combination of layout and process. The basic idea, as with all modeling, is to enable experiments to be done quickly and efficiently. Since the alternative is to actually build chips and then take measurements, which is millions of dollars of investment and months of delay, the virtual fabrication route is especially attractive. This is especially important in the early stages of process development since it can drastically shorten the whole development and ramp to volume roadmap.
by Pawan Fangaria
Although MEMS devices in various forms are now found in most electronic devices, predominantly in mobile, automotive, aerospace and many other applications, their major revolution, I believe, is yet to happen. We are seeing rapid innovation in MEMS reflected by their improvements in precision, performance, size reduction, and the continuing evolution of new devices with increasing complexities. The micro level fabrication of MEMS will enable unprecedented use of these into newer and newer semiconductor based electronic devices that will revolutionize the so called IoT arena. MEMS will be essential to IoT products’ ability to connect every aspect of our life, things and happenings around us and provide us ultimate knowledge, control, security through a wide range of devices in many form factors and environments.
The NAND flash business is transitioning from the process that has been used for the past 20-odd years (let’s call it “2D”) and the new process that promises to carry the technology through the end of the decade: 3D NAND.
Trouble is: 3D NAND is bearishly tough to manufacture. This is clear from the fact that Samsung announced “Mass Production” of its VNAND rendition of 3D NAND last August, yet these chips are as rare as hen’s teeth in the marketplace today. Other companies haven’t gone so far as to announce production, and have been very conservative in their predictions of when they plan to roll out their own 3D NAND chips. Most plan to sample late this year or in 2015, and to enter production a year or so later.