Press Coverage

IEDM: Coventor Panel on BEOL Challenges

By Paul McLellan

At the recent IEDM in San Francisco, Coventor organized a panel titled BEOL Barricades: Navigating Future Semiconductor Yield, Reliability, and Cost Challenges. The BEOL, back end of line, is the metal, although where it begins and ends, as you will see, is debatable.

The panel was moderated by Ed Sperling and the panelists were:

  • Paul Besser of LAM Research
  • Chih-Chien Liu of UMC
  • Craig Child of GLOBALFOUNDRIES
  • Anton deVilliers of Tokyo Electron
  • David Fried of Coventor

 

read the full article here.

Uncertainty Grows For 5nm, 3nm

By Mark Lapedus

As several chipmakers ramp up their 10nm finFET processes, with 7nm just around the corner, R&D has begun for 5nm and beyond. In fact, some are already moving full speed ahead in the arena.

TSMC recently announced plans to build a new fab in Taiwan at a cost of $15.7 billion. The proposed fab is targeted to manufacture TSMC’s 5nm and 3nm processes, which are due out in 2020 and 2022, respectively. Other chipmakers, including GlobalFoundries, Intel and Samsung, also are looking at technologies for 5nm and beyond.

read the full article here.

IEDM 2016 Next Week – Siliconica

By Dick James, Senior Technology Analyst, Chipworks

On December 3rd – 7th , the good and the great of the electron device world will make their usual pilgrimage to San Francisco for the 2016 IEEE International Electron Devices Meeting. To quote the conference website front page, IEDM is “is the world’s preeminent forum for reporting technological breakthroughs in the areas of semiconductor and electronic device technology, design, manufacturing, physics, and modeling. IEDM is the flagship conference for nanometer-scale CMOS transistor technology, advanced memory, displays, sensors, MEMS devices, novel quantum and nano-scale devices and phenomenology, optoelectronics, devices for power and energy harvesting, high-speed devices, as well as process technology and device modeling and simulation.”

That’s a pretty broad range of topics, but from my perspective at Chipworks, focused on the analysis of chips that have made it to production, it’s the conference where companies strut their technology, and post some of the research that may make it into real product in the next few years. Though these days process papers actually tend to be after the launch of the relevant product, such is the preoccupation with trade secrecy.

read the full article here.

Driverless Vehicle Makers, Carriers, Drone-Defense Creators Look to MEMS & Sensors Industry for Advanced Sensing and Actuation

By Chip Design

MEMS & Sensors Industry Group (MSIG)’s MEMS & Sensors Executive Congress™ — held November 9-11 in Scottsdale, AZ — gave innovative developers of driverless vehicles and drone-defense makers — as well as one of the world’s top carriers — a ready audience of industry execs as they shared their wants for new MicroElectroMechanical Systems (MEMS)/sensors for future products.

Phillip M. Rayer II, general manager, Local Motors, described how his company uses “co-creation” — involving as many as 50,000 developers — to design driverless electric vehicles for target communities. Local Motors uses 3D printing to manufacture the vehicles in months rather than years.

read the full article here.

Audio and Sensor Integration Extracting Themes from the MEMS Executive Congress

By Bryon Moyer

If it’s November, that means it’s time for the C-level folks in the MEMS and sensor industries to assemble and assess the state of the industry at the MEMS Executive Congress. Because of the higher average title of these attendees, it has a very different feel from other conferences. And it mostly happens in lockstep (without five different tracks and an exhibit floor as distractions). Which makes it a bit easier to get a read on things.

It wasn’t so long ago when the theme of the year would typically focus on individual new MEMS structures – especially for motion. Then came the wave of sensor fusion – again, largely motion-oriented, but with promise beyond that, at least as a concept. Most of the more visible independent sensor fusion companies then were acquired, and the last few editions of the Congress have had less of the, “OMG, we’ve arrived!” feel and more of the, “Takin’ care of business” feel.

read the full article here.

Photonics 3-D Modeler Born – Coventor Aims at Future Optics

By R. Colin Johnson

LAKE WALES, Fla. — Coventor’s SEMulator3D began as a tool for designing microelectromechanical systems (MEMS), then evolved to semiconductor equipment companies, chip makers and foundries for the 3-D structures in FinFETS, 3-D NAND and HD disk-heads. Now every major company in the MEMS and semiconductor supply chain uses Coventor’s tools (with over half of their customers making semiconductors instead of MEMS). Next Coventor is anticipating the mixed analog/digital/photonic chips of the future by adding modeling of the optical channels, mixers, and other specialized functions for the coming photonic era.

read the full article here.

Can We Measure Next-Gen FinFETs?

By Mark Lapedus

After ramping up their respective 16nm/14nm finFET processes, chipmakers are moving towards 10nm and/or 7nm, with 5nm in R&D. But as they move down the process roadmap, they will face a new set of fab challenges. In addition to lithography and interconnects, there is metrology.

Metrology, the science of measurements, is used to characterize tiny films and structures. It helps to boost yields and prevent defects in the fab, which in turn impacts the overall cost for chipmakers. At advanced nodes, though, metrology is becoming more complex, challenging and expensive. And there are a growing number of gaps in metrology, especially for finFETs at 10nm and beyond.

read the full article here.

Why EUV Is So Difficult

By Mark Lapedus

For years, extreme ultraviolet (EUV) lithography has been a promising technology that was supposed to help enable advanced chip scaling. But after years of R&D, EUV is still not in production despite major backing from the industry, vast resources and billions of dollars in funding.

More recently, though, EUV lithography appears to be inching closer to possible insertion for high-volume manufacturing, at least for one or a few critical layers. Two chipmakers, Intel and Samsung, have put EUV on their roadmaps at 7nm in the 2018 or 2019 timeframe. In addition, Samsung hopes to use EUV for 1xnm DRAMs.