by Pawan Fangaria
Published in SemiWiki
Ever since I started talking about Virtual Fabrication I have mostly looked at it from the manufacturers’ perspective, where it has obvious benefits to develop and model new process technology. But what about the fabless design concept and indeed even the semiconductor IP world that has spawned from it as well? It seems that Virtual Fabrication could be very effective to gain confidence in the fabrication of design by a fabless company, before it sees the actual foundry. Just think about this and in the meanwhile let’s briefly reflect on the evolution of fabless design concept.
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by Bryon Moyer
April 16, 2014 at 11:08 AM
Coventor recently released a new version of SEMulator 3D. We’ve looked at this tool before; it’s what they call a virtual fabrication platform – helpful for simulating semiconductor processes.
Featured in this upgrade is an improvement in the modeling of so-called pattern-dependent etch effects. In other words, how an etch proceeds at one spot depends on what’s around it. And looking farther out apparently makes for a more accurate simulation result, so, with this release, they’ve increased the radius that defines the region or neighborhood to be evaluated when assessing what the local layout looks like.
They’ve also sped up their etch simulation in general.
Meanwhile, they’ve more fully productized a couple of existing features. One is a structure search capability. This allows the user to find a specific structure in all of the various models. This can be particularly useful, for example, when you learn about some particular yield-impacting configuration and want to figure out which models it affects.
by Pawan Fangaria
MEMS design and fabrication is highly complex in the sense that the fabrication process heavily depends on the design, unlike IC fabrication which has a standard set of processes. A slight change in MEMS design can alter its fabrication steps to a large extent. For example, setting device parameters such as capacitance or linear displacement can affect the choice of the film thickness, etch rate, sidewall profile and so on. The design and process are so much tied together that many iterations through the fab are required (which consume costly resources and time) in order to get a perfect build. While an IDM has to keep its fab resources deployed for such a build-and-test experimentation in-house, a fabless design house has to additionally incur time for its design to take several tours through an external fab. This all has significant impact, first on cost of design and manufacturing and then turn-around-time, thus squeezing the window of opportunity which is already small in today’s competitive semiconductor market. read more…
Not everyone is sticking on the Moore’s Law path. Experts across the industry are expecting big changes, starting this year.
Last week, Semiconductor Engineering examined the 2014 predictions from several thought leaders in the industry and published those predictions that related to general market trends. Many of those predictions require some advances in semiconductor technologies and fabrications capabilities. It is those predictions that will be examined in this part, followed next week by the predictions related to design, verification and implementation tools.
There is a large amount of agreement in the industry about the macro trends for semiconductors this year. They fall into three main categories:
- Migration to new processing nodes.
- Adoption of FinFETs.
- Increasing utilization of 2.5D and 3D integration.
When we couple these with the general market trends, there could be significant changes ahead for the industry. read more…
by Pawan Fangaria
The design and manufacture of MEMS is very different and in many ways more complex process than even the most advanced ICs. MEMS involve multiple degrees of freedom (i.e. the device to exhibit different characteristics under different physical state, motion or mechanics), making fabrication of MEMS extremely complex; and hence the processes are highly customized and typically linked to particular design or device. The process flow and design parameters are highly sensitive to each other, thus requiring multiple build-and-test cycles and longer MEMS process learning cycles. And these days most of electronic devices or semiconductor designs involve MEMS integrated into them, necessitating a MEMS+IC design approach. For example, gyroscopes are being used in smartphones in big way to enhance motion detection and orientation. Given the cut-throat competition in the mobile market, with increasing feature sets and shrinking windows of opportunity, it’s critical that process learning cycles for MEMS development move from time-consuming build-and-test methods to more efficient methodologies to streamline the handoff from design to manufacturing.
The good news is that Coventor’s SEMulator3D tool (about which I had earlier talked in the context of Virtual Fabrication Platform for semiconductor design ICs) is providing an excellent platform for virtual modeling of MEMS as well. Physical data (such as capacitance) can be extracted from the model for quantitative analysis and process variation studied to quickly predict the exact model of interest before actual fabrication, thus reducing the learning cycle for MEMS.
by Pawan Fangaria
As I see the semiconductor industry going through significant changes and advances, yet ironically plagued by a growing perception that the pace of scaling is slowing, I was inclined to take a peek into what the industry experts say about the state of the industry and the future of Moore’s Law. Fortunately, at last week’s International Electron Devices Meeting (IEDM 2013), a panel discussion among an impressive lineup of experts from industry leading organizations was set up. Dr. David M. Fried, CTO-Semiconductor at Coventor, the host organization, moderated the session.
MEMS design software gets 64-bit upgrade Version 4.0 of the MEMS+ design software from Coventor Inc. (Cary, North Carolina) is a full 64-bit implementation that adds the ability to export Verilog-A models.
The 64-bit resolution allows more accurate modeling of MEMS sensors and actuators and the software is designed to operate in parallel with Matlab and Virtuoso design software from Mathworks and Cadence Design Systems Inc., respectively.
The extension to 64-bits has been accompanied by an option to tune the software between accuracy and speed. Reduced-order models can be exported in Verilog-A format, for use by IC designers. These exported models simulate 100X faster than fully non-linear MEMS+ models and are compatible with all commercial analog/mixed-signal circuit simulators that support the industry-standard Verilog-A hardware description language.
by George Leopold on December 16, 2013
WASHINGTON, D.C. — The job of making advanced chips and finding ways to collaborate on the work is getting tougher, according to a panel of veteran semiconductor researchers who gathered just outside the International Electron Devices Meeting in Washington last week.
Moderator David Fried, chief technologist of Coventor, a supplier of 3D modeling and simulation software, asked panelists to describe the biggest technical challenges they face as well as the key challenges to keeping their projects on schedule. The latter question is critical, given the growing industry perception that the pace of chip scaling is slowing. That is making it harder for IC makers to push designs based on ever-shrinking geometries out the door.