Press Coverage

The Road Ahead for 2014: Semiconductors

Semiconductor Engineering
Not everyone is sticking on the Moore’s Law path. Experts across the industry are expecting big changes, starting this year.

Last week, Semiconductor Engineering examined the 2014 predictions from several thought leaders in the industry and published those predictions that related to general market trends. Many of those predictions require some advances in semiconductor technologies and fabrications capabilities. It is those predictions that will be examined in this part, followed next week by the predictions related to design, verification and implementation tools.

There is a large amount of agreement in the industry about the macro trends for semiconductors this year. They fall into three main categories:

  • Migration to new processing nodes.
  • Adoption of FinFETs.
  • Increasing utilization of 2.5D and 3D integration.

When we couple these with the general market trends, there could be significant changes ahead for the industry. read more…

Quick MEMS Development Through Virtual Fabrication

by Pawan Fangaria

The design and manufacture of MEMS is very different and in many ways more complex process than even the most advanced ICs. MEMS involve multiple degrees of freedom (i.e. the device to exhibit different characteristics under different physical state, motion or mechanics), making fabrication of MEMS extremely complex; and hence the processes are highly customized and typically linked to particular design or device. The process flow and design parameters are highly sensitive to each other, thus requiring multiple build-and-test cycles and longer MEMS process learning cycles. And these days most of electronic devices or semiconductor designs involve MEMS integrated into them, necessitating a MEMS+IC design approach. For example, gyroscopes are being used in smartphones in big way to enhance motion detection and orientation. Given the cut-throat competition in the mobile market, with increasing feature sets and shrinking windows of opportunity, it’s critical that process learning cycles for MEMS development move from time-consuming build-and-test methods to more efficient methodologies to streamline the handoff from design to manufacturing.

The good news is that Coventor’s SEMulator3D tool (about which I had earlier talked in the context of Virtual Fabrication Platform for semiconductor design ICs) is providing an excellent platform for virtual modeling of MEMS as well. Physical data (such as capacitance) can be extracted from the model for quantitative analysis and process variation studied to quickly predict the exact model of interest before actual fabrication, thus reducing the learning cycle for MEMS.

read more…

Semicon Technology Advancement – A View From IEDM

by Pawan Fangaria

As I see the semiconductor industry going through significant changes and advances, yet ironically plagued by a growing perception that the pace of scaling is slowing, I was inclined to take a peek into what the industry experts say about the state of the industry and the future of Moore’s Law. Fortunately, at last week’s International Electron Devices Meeting (IEDM 2013), a panel discussion among an impressive lineup of experts from industry leading organizations was set up. Dr. David M. Fried, CTO-Semiconductor at Coventor, the host organization, moderated the session.
read more…

MEMS design software gets 64-bit upgrade

Peter Clarke

MEMS design software gets 64-bit upgrade Version 4.0 of the MEMS+ design software from Coventor Inc. (Cary, North Carolina) is a full 64-bit implementation that adds the ability to export Verilog-A models.

The 64-bit resolution allows more accurate modeling of MEMS sensors and actuators and the software is designed to operate in parallel with Matlab and Virtuoso design software from Mathworks and Cadence Design Systems Inc., respectively.

The extension to 64-bits has been accompanied by an option to tune the software between accuracy and speed. Reduced-order models can be exported in Verilog-A format, for use by IC designers. These exported models simulate 100X faster than fully non-linear MEMS+ models and are compatible with all commercial analog/mixed-signal circuit simulators that support the industry-standard Verilog-A hardware description language.
read more…

Panel Probes Chipmaking Challenges

EE Times
by George Leopold on December 16, 2013

WASHINGTON, D.C. — The job of making advanced chips and finding ways to collaborate on the work is getting tougher, according to a panel of veteran semiconductor researchers who gathered just outside the International Electron Devices Meeting in Washington last week.

Moderator David Fried, chief technologist of Coventor, a supplier of 3D modeling and simulation software, asked panelists to describe the biggest technical challenges they face as well as the key challenges to keeping their projects on schedule. The latter question is critical, given the growing industry perception that the pace of chip scaling is slowing. That is making it harder for IC makers to push designs based on ever-shrinking geometries out the door.

Read more

Q&A: MEMS Begin to Enter the Semiconductor Design Mainstream
By Richard Goering on December 11, 2013

Micro-electrical mechanical systems (MEMS) have been a niche technology for many years, but a new generation of MEMS ICs is emerging, according to Mike Jamiolkowski, CEO of Cadence partner and MEMS tool provider Coventor. Barriers to the use of MEMS technology, such as the need for PhD-level experts and non-reusable foundry processes, are starting to ease.

In this interview Jamiolkowski talks about new trends in the MEMS market, discusses his company’s MEMS+ tools and how they work with the Cadence Virtuoso platform, and notes a new MEMS+ capability to output reduced order models in the Verilog-A language.
read more…

Lithography challenges threaten the cost benefits of IC scaling

By David Fried
Tech Design Forum

Will we be able to engineer another technology node that brings the usual cost and area savings without EUV lithography? I have serious doubts.

EUV lithography was supposed to be ready for the 45nm process node, and was then delayed until 32nm and later, 22nm. Today, major semiconductor companies are continuing to develop their offerings. Some will use the upcoming IEDM to detail their 1xnm processes, developed despite the lack of EUV’s patterning capabilities.

Why the delay with EUV? The story has been told many times: a combination of complex electro-optics, problems with the power of the illumination source, resist sensitivity and defectivity. The list of EUV challenges is long, but the summary is short: it’s not ready yet!
read more…

Catching Up With Steve Breit, Coventor, at the TSensors Summit

By Paul Werbaneth

A journey of a trillion sensors begins with a single step.

The TSensors Summit, held at Stanford University on 23 – 25 October 2013, was a showcase for the ideas and strategies that will lead the electronics industry to produce very high volumes of Microelectromechanical Systems (MEMS)-based sensors for use in new applications likely to enter the market in the coming decade.

There are currently several mega platform markets for MEMS sensors (and for the application-specific integrated circuits (ASIC), used to interface with them); most notable of these mega platform markets are smartphones, tablets, automobiles, and handheld consumer electronics products. Together, along with all other markets for MEMS sensors, the unit volume of MEMS devices shipped in 2013 will be on the order of billions, or the low tens of billions. (Nowhere close, yet, to 1 trillion.)
read more…