Press Coverage

Simpler MEMS Models for ASIC Designers

by Bryon Moyer
October 31, 2013 at 3:07 PM

Some time back, we took a look at the library of mechanical elements in Coventor’s MEMS+ tool for building MEMS device models. In the “be careful what you wish for” category, making it easier to connect elements into models meant that engineers started connecting more elements into models, and the models got bigger.

Big models can stress a tool out, resulting in slow results and resource starvation.

Well, they’ve just released version 4 of MEMS+, which at the very start, addresses those concerns, enabling quicker handling of more complex models.

But there’s a much more subtle way that they’ve addressed the needs of ASIC designers. Each MEMS element will need an accompanying ASIC to clean up the signals and abstract away a lot of the mechanicalness of the element so that electrical types – or, more likely, digital types – can understand the sensor outputs in their own language.

And, of course, you’re going to want to get started on that ASIC design as soon as possible. But the whole purpose of the ASIC is to turn messy sense element behavior into clean outputs, and in order to do that, you need to know exactly what messy signals you’re going to start with. And you don’t want to wait until the device is finished to do that; you want to model the behavior ahead of time.
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What Can Accelerate 3D Semiconductor Manufacturing?

by Pawan Fangaria
Semiwiki.com
Published on 10-12-2013 07:30 AM

In the beginning of this decade there was a lot of buzz around 3D chip manufacturing. Many EDA tools were developed to facilitate semiconductor designs in 3D space. Naturally, we are moving to the edge on 2D without much room to further squeeze transistors and interconnect. However, lately I haven’t heard much about 3D products. What happened? All I could guess is that there must be manufacturing difficulties, yield and ramp-up issues and the like. Then, last week I got to hear from IHS iSuppli that NAND Flash memories are moving into 3D manufacturing. That was interesting news, so I looked further into one of the latest articles on iSuppli website written by Dee Robinson, here. It’s understandable because NAND Flash memory is the fastest in reaching that limit of finer geometry in 2D production, however I was disappointed after learning that 3D NAND Flash will take four years from now to reach about 65% (by 2017) of total NAND Flash share. Why should it take so long? read more…

Rapid Yield Optimization at 22nm Through Virtual Fab

SemiWiki.com
by Pawan Fangaria

Remember? During DAC 2013 I talked about a new kind of innovation: A Virtual Fabrication Platform, SEMulator3D, developed by COVENTOR. Now, to my pleasant surprise, there is something to report on the proven results from this platform. IBM, in association with COVENTOR, has successfully implemented a 3D Virtual Fabrication methodology to rapidly improve the yield of high performance 22nm SOI CMOS technology.

The CTO-Semiconductor of COVENTOR, Dr. David M. Fried was in attendance while IBM’s Ben Cipriany presented an interesting paper on this work at The International Conference on Simulation of Semiconductor Processes and Devices (SISPAD 2013). The paper is available at the link “IBM, Coventor present 22nm Virtual Fabrication Success at SISPAD” at the COVENTOR website.

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Coventor launches ‘Virtual fabrication’ software

Micro Manufacturing

Coventor Inc., a supplier of virtual fabrication solutions for semiconductor devices and micro-electromechanical systems (MEMS), announced the availability of its SEMulator3D 2013 “virtual fabrication” software platform.

SEMulator3D 2013 offers physical accuracy and predictive modeling capabilities to process development and integration, according to the company. The software makes “virtual fabrication” available to the broader semiconductor ecosystem, helping reduce silicon learning cycles and the billions of dollars spent reaching manufacturing readiness, the Cary, N.C.-based company reports.

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Conventor’s CTO Dr. David Fried to Discuss 3D Virtual Fabrication Break Through at Semicon West 2013 Conference

EE Journal

CARY, North Carolina – June 26, 2013 – Coventor®, Inc., the leading supplier of virtual fabrication solutions for semiconductor devices and micro-electromechanical systems (MEMS), will participate in SEMICON West 2013 in San Francisco, CA from July 9 to July 11, 2013 with a featured technical presentation by Coventor’s CTO Dr. David Fried and live software demonstrations that showcase the latest ‘virtual fabrication’ innovations aimed at significantly reducing the silicon learning cycles and billions of dollars spent reaching manufacturing readiness for integrated 3D processes.

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New Process Modeling Mechanism

by Bryon Moyer
EE Journal

Simulation is all about using the simplest possible modeling technique that gives enough accuracy to make the results useful. Simplicity typically speeds up simulation – and, in many cases, makes the problem tractable in the first place.

But at some point, the unnecessary details that the modeling abstractions hide become necessary. At that stage, if you’re lucky, you can tweak your modeling technique to allow for the now-important effects. But eventually you may to have to take a new approach.

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