Press Coverage

What Happened To Inverse Lithography?

By Mark Lapedus

Nearly 10 years ago, the industry rolled out a potentially disruptive technique called inverse lithography technology (ILT). But ILT was ahead of its time, causing the industry to push out the technology and relegate it to niche-oriented applications.

Today, though, ILT is getting new attention as the semiconductor industry pushes toward 7nm, and perhaps beyond. ILT is not a next-generation lithography (NGL) tool technology. Instead it falls into the field of computational lithography and is used for the production of advanced photomasks.

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Foundries See Mixed Future

By Mark Lapedus

Amid a tumultuous business environment, the silicon foundry industry is projected to see steady growth in a number of process segments in 2017.

As in past years, the foundry market is expected to grow faster than the overall IC industry in 2017. But at the same time, the IC industry—the foundry customer base—continues to witness a frenetic wave of merger and acquisition activity. Basically, the consolidation translates into a dwindling customer base for foundry vendors.

Adding to the uncertainty is a mixed picture for the overall IC market in 2017, plus some possible instability in the current economic and political climate.

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Mask Maker Worries Grow

By Mark Lapedus

Photomasks are becoming more complex and expensive at each node, thereby creating a number of challenges on several fronts.

For one thing, the features on the photomask are becoming smaller and more complex at each node. Second, the number of masks per mask-set are increasing as a result of multiple patterning. Third, it costs more to build and equip a new mask fabrication facility. And finally, mask tool costs are soaring at each node.

To find out what’s required for future masks, Semiconductor Engineering recently conducted an informal poll among several photomask experts. The poll asked experts to come up with a “wish list” of technologies that are required for future mask making.

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Sorting Out Next-Gen Memory

By Mark Lapedus

In the data center and related environments, high-end systems are struggling to keep pace with the growing demands in data processing.

There are several bottlenecks in these systems, but one segment that continues to receive an inordinate amount of attention, if not part of the blame, is the memory and storage hierarchy.

SRAM, the first tier of this hierarchy, is integrated into the processor for cache to enable fast data access. Then, DRAM, the next tier in the hierarchy, is used for main memory. And finally, disk drives and NAND-based solid-state storage drives (SSDs) are used for storage.

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Faster Time To Yield

By Ed Sperling

Coventor’s CEO talks about how to get chips through manufacturing more quickly.

Michael Jamiolkowski, president and CEO of Coventor, sat down with Semiconductor Engineering to talk about ways improve yield ramp and optimize designs. What follows are excerpts of that conversation.

SE: Why does it take so long to get a chip all the way through to manufacturing?

MikeJJamiolkowski: There are three parts to that. There is a research side. You want to be able to explore new things and possibilities. There is the manufacturing side, which is going to take the normal amount of time for getting things ramped up. And then there is the ‘in-between’ phase—the technology development. It may take four years before a product reaches the market. That ‘in-between’ phase is where a lot of the hard work gets done, using a lot of short loop and learning cycles. You’re not just trying to create one device. You’re trying to create a billion devices. You are trying to use that process to address different types of structures, not just for one finFET or memory, but all the complexities and devices that might go into that process, as well. Then you have the BEOL and such. There is a lot of work that is going on during those four years. Traditionally, the way things worked was that it was these short loop cycles of one to three months. Then there were test chips, which might be out once per year. But it would take about three or four of those one-year cycles to be able to get them through, along with lots of the little cycles of learning. Our customers believe they can change this ‘in-between’ period to reduce the amount of time. We had a customer that did these virtual fabrications and cut nine months out of their development cycle.

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What Transistors Will Look Like At 5nm

By Mark Lapedus

Chipmakers are currently ramping up 16nm/14nm finFET processes, with 10nm and 7nm just around the corner.

The industry also is working on 5nm. TSMC hopes to deliver a 5nm process by 2020. GlobalFoundries, Intel and Samsung are doing R&D for that node.

But 5nm technology presents a multitude of unknowns and challenges. For one thing, the exact timing and specs of 5nm remain cloudy. Then, there are several technical and economic roadblocks. And even if 5nm happens, it’s likely that only a few companies will be able to afford it.

“My current assumption is that 5nm will happen, but it won’t hit high-volume manufacturing until after 2020,” said Bob Johnson, an analyst at Gartner. “If I were to guess, I’d say 2021 to 2022.”

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IMEC Technology Forum at SEMICON – Coventor could save you billions!

semiwiki-logoBy Scotten Jones

The development of leading edge semiconductor technology is incredibly expensive, with estimates ranging from a few to several billion dollars for new nodes. The time to develop a leading edge process is also a critical competitive issue with some of the largest opportunities awarded based on who is first to yield on a new node.

Being late to market can cost a semiconductor company billions of dollars in lost opportunities! Coventor produces SEMulator3D, a modeling platform that enables development engineers to simulate process flows in full 3D to test and refine them before running wafers, reducing development costs and speeding up time to market. David Fried is the CTO of Coventor and he presented at the IMEC Technology Forum (ITF) on Monday before SEMICON. I was at David’s presentation and I also had the opportunity to interview him on Wednesday during the show.

read the full article here.

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Industry Award for Coventor

Silicon Semiconductor Logo Coventor, Inc., supplier of automated software solutions for semiconductor devices and micro-electromechanical systems (MEMS), has announced its SEMulator3D 6.0 won the 2016 “Best of the West” award sponsored by Solid State Technology and SEMI at SEMICON West. This industry award recognizes the product and technology developments that contributed the most significant improvements to the electronics manufacturing supply chain. Coventor’s SEMulator3D was selected for the significant financial, scientific and social impact it has had on the industry.

Coventor’s SEMulator3D is a 3D virtual fabrication platform that predictively models how next-generation processes including FinFETs, 3D NAND Flash, BEOL, Nanowires, 3D-IC, FDSOI, and DRAM will perform in the fab. Combining design data with advanced physics and deep process knowledge, SEMulator3D creates a “virtual” silicon wafer and mimics a series of unit processes like those in the fab resulting in highly-accurate 3D computer models of the predicted structures on wafer.

read the full article here.