Press Coverage

Photonics 3-D Modeler Born – Coventor Aims at Future Optics

By R. Colin Johnson

LAKE WALES, Fla. — Coventor’s SEMulator3D began as a tool for designing microelectromechanical systems (MEMS), then evolved to semiconductor equipment companies, chip makers and foundries for the 3-D structures in FinFETS, 3-D NAND and HD disk-heads. Now every major company in the MEMS and semiconductor supply chain uses Coventor’s tools (with over half of their customers making semiconductors instead of MEMS). Next Coventor is anticipating the mixed analog/digital/photonic chips of the future by adding modeling of the optical channels, mixers, and other specialized functions for the coming photonic era.

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Can We Measure Next-Gen FinFETs?

By Mark Lapedus

After ramping up their respective 16nm/14nm finFET processes, chipmakers are moving towards 10nm and/or 7nm, with 5nm in R&D. But as they move down the process roadmap, they will face a new set of fab challenges. In addition to lithography and interconnects, there is metrology.

Metrology, the science of measurements, is used to characterize tiny films and structures. It helps to boost yields and prevent defects in the fab, which in turn impacts the overall cost for chipmakers. At advanced nodes, though, metrology is becoming more complex, challenging and expensive. And there are a growing number of gaps in metrology, especially for finFETs at 10nm and beyond.

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Why EUV Is So Difficult

By Mark Lapedus

For years, extreme ultraviolet (EUV) lithography has been a promising technology that was supposed to help enable advanced chip scaling. But after years of R&D, EUV is still not in production despite major backing from the industry, vast resources and billions of dollars in funding.

More recently, though, EUV lithography appears to be inching closer to possible insertion for high-volume manufacturing, at least for one or a few critical layers. Two chipmakers, Intel and Samsung, have put EUV on their roadmaps at 7nm in the 2018 or 2019 timeframe. In addition, Samsung hopes to use EUV for 1xnm DRAMs.

What Happened To Inverse Lithography?

By Mark Lapedus

Nearly 10 years ago, the industry rolled out a potentially disruptive technique called inverse lithography technology (ILT). But ILT was ahead of its time, causing the industry to push out the technology and relegate it to niche-oriented applications.

Today, though, ILT is getting new attention as the semiconductor industry pushes toward 7nm, and perhaps beyond. ILT is not a next-generation lithography (NGL) tool technology. Instead it falls into the field of computational lithography and is used for the production of advanced photomasks.

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Foundries See Mixed Future

By Mark Lapedus

Amid a tumultuous business environment, the silicon foundry industry is projected to see steady growth in a number of process segments in 2017.

As in past years, the foundry market is expected to grow faster than the overall IC industry in 2017. But at the same time, the IC industry—the foundry customer base—continues to witness a frenetic wave of merger and acquisition activity. Basically, the consolidation translates into a dwindling customer base for foundry vendors.

Adding to the uncertainty is a mixed picture for the overall IC market in 2017, plus some possible instability in the current economic and political climate.

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Mask Maker Worries Grow

By Mark Lapedus

Photomasks are becoming more complex and expensive at each node, thereby creating a number of challenges on several fronts.

For one thing, the features on the photomask are becoming smaller and more complex at each node. Second, the number of masks per mask-set are increasing as a result of multiple patterning. Third, it costs more to build and equip a new mask fabrication facility. And finally, mask tool costs are soaring at each node.

To find out what’s required for future masks, Semiconductor Engineering recently conducted an informal poll among several photomask experts. The poll asked experts to come up with a “wish list” of technologies that are required for future mask making.

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Sorting Out Next-Gen Memory

By Mark Lapedus

In the data center and related environments, high-end systems are struggling to keep pace with the growing demands in data processing.

There are several bottlenecks in these systems, but one segment that continues to receive an inordinate amount of attention, if not part of the blame, is the memory and storage hierarchy.

SRAM, the first tier of this hierarchy, is integrated into the processor for cache to enable fast data access. Then, DRAM, the next tier in the hierarchy, is used for main memory. And finally, disk drives and NAND-based solid-state storage drives (SSDs) are used for storage.

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Faster Time To Yield

By Ed Sperling

Coventor’s CEO talks about how to get chips through manufacturing more quickly.

Michael Jamiolkowski, president and CEO of Coventor, sat down with Semiconductor Engineering to talk about ways improve yield ramp and optimize designs. What follows are excerpts of that conversation.

SE: Why does it take so long to get a chip all the way through to manufacturing?

MikeJJamiolkowski: There are three parts to that. There is a research side. You want to be able to explore new things and possibilities. There is the manufacturing side, which is going to take the normal amount of time for getting things ramped up. And then there is the ‘in-between’ phase—the technology development. It may take four years before a product reaches the market. That ‘in-between’ phase is where a lot of the hard work gets done, using a lot of short loop and learning cycles. You’re not just trying to create one device. You’re trying to create a billion devices. You are trying to use that process to address different types of structures, not just for one finFET or memory, but all the complexities and devices that might go into that process, as well. Then you have the BEOL and such. There is a lot of work that is going on during those four years. Traditionally, the way things worked was that it was these short loop cycles of one to three months. Then there were test chips, which might be out once per year. But it would take about three or four of those one-year cycles to be able to get them through, along with lots of the little cycles of learning. Our customers believe they can change this ‘in-between’ period to reduce the amount of time. We had a customer that did these virtual fabrications and cut nine months out of their development cycle.

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