by George Leopold on December 16, 2013
WASHINGTON, D.C. — The job of making advanced chips and finding ways to collaborate on the work is getting tougher, according to a panel of veteran semiconductor researchers who gathered just outside the International Electron Devices Meeting in Washington last week.
Moderator David Fried, chief technologist of Coventor, a supplier of 3D modeling and simulation software, asked panelists to describe the biggest technical challenges they face as well as the key challenges to keeping their projects on schedule. The latter question is critical, given the growing industry perception that the pace of chip scaling is slowing. That is making it harder for IC makers to push designs based on ever-shrinking geometries out the door.
By Richard Goering on December 11, 2013
Micro-electrical mechanical systems (MEMS) have been a niche technology for many years, but a new generation of MEMS ICs is emerging, according to Mike Jamiolkowski, CEO of Cadence partner and MEMS tool provider Coventor. Barriers to the use of MEMS technology, such as the need for PhD-level experts and non-reusable foundry processes, are starting to ease.
In this interview Jamiolkowski talks about new trends in the MEMS market, discusses his company’s MEMS+ tools and how they work with the Cadence Virtuoso platform, and notes a new MEMS+ capability to output reduced order models in the Verilog-A language.
By David Fried
Tech Design Forum
Will we be able to engineer another technology node that brings the usual cost and area savings without EUV lithography? I have serious doubts.
EUV lithography was supposed to be ready for the 45nm process node, and was then delayed until 32nm and later, 22nm. Today, major semiconductor companies are continuing to develop their offerings. Some will use the upcoming IEDM to detail their 1xnm processes, developed despite the lack of EUV’s patterning capabilities.
Why the delay with EUV? The story has been told many times: a combination of complex electro-optics, problems with the power of the illumination source, resist sensitivity and defectivity. The list of EUV challenges is long, but the summary is short: it’s not ready yet!
By Paul Werbaneth
A journey of a trillion sensors begins with a single step.
The TSensors Summit, held at Stanford University on 23 – 25 October 2013, was a showcase for the ideas and strategies that will lead the electronics industry to produce very high volumes of Microelectromechanical Systems (MEMS)-based sensors for use in new applications likely to enter the market in the coming decade.
There are currently several mega platform markets for MEMS sensors (and for the application-specific integrated circuits (ASIC), used to interface with them); most notable of these mega platform markets are smartphones, tablets, automobiles, and handheld consumer electronics products. Together, along with all other markets for MEMS sensors, the unit volume of MEMS devices shipped in 2013 will be on the order of billions, or the low tens of billions. (Nowhere close, yet, to 1 trillion.)
by Pawan Fangaria
The growing process integration complexity at each technology node has increased development time and cost, and this trend looks to continue. There is a looming risk of delivering unrepeatable critical unit processes (or process modules) that would require revisiting development and manufacturing requalification or in severe cases a design re-spin. Below the 22nm process node, tremendous effort is necessary to meet process integration specifications with a yielding process that is robust in the face of unavoidable manufacturing variation. read more…
by Bryon Moyer
October 31, 2013 at 3:07 PM
Some time back, we took a look at the library of mechanical elements in Coventor’s MEMS+ tool for building MEMS device models. In the “be careful what you wish for” category, making it easier to connect elements into models meant that engineers started connecting more elements into models, and the models got bigger.
Big models can stress a tool out, resulting in slow results and resource starvation.
Well, they’ve just released version 4 of MEMS+, which at the very start, addresses those concerns, enabling quicker handling of more complex models.
But there’s a much more subtle way that they’ve addressed the needs of ASIC designers. Each MEMS element will need an accompanying ASIC to clean up the signals and abstract away a lot of the mechanicalness of the element so that electrical types – or, more likely, digital types – can understand the sensor outputs in their own language.
And, of course, you’re going to want to get started on that ASIC design as soon as possible. But the whole purpose of the ASIC is to turn messy sense element behavior into clean outputs, and in order to do that, you need to know exactly what messy signals you’re going to start with. And you don’t want to wait until the device is finished to do that; you want to model the behavior ahead of time.
by Pawan Fangaria
Published on 10-12-2013 07:30 AM
In the beginning of this decade there was a lot of buzz around 3D chip manufacturing. Many EDA tools were developed to facilitate semiconductor designs in 3D space. Naturally, we are moving to the edge on 2D without much room to further squeeze transistors and interconnect. However, lately I haven’t heard much about 3D products. What happened? All I could guess is that there must be manufacturing difficulties, yield and ramp-up issues and the like. Then, last week I got to hear from IHS iSuppli that NAND Flash memories are moving into 3D manufacturing. That was interesting news, so I looked further into one of the latest articles on iSuppli website written by Dee Robinson, here. It’s understandable because NAND Flash memory is the fastest in reaching that limit of finer geometry in 2D production, however I was disappointed after learning that 3D NAND Flash will take four years from now to reach about 65% (by 2017) of total NAND Flash share. Why should it take so long? read more…
by Pawan Fangaria
Remember? During DAC 2013 I talked about a new kind of innovation: A Virtual Fabrication Platform, SEMulator3D, developed by COVENTOR. Now, to my pleasant surprise, there is something to report on the proven results from this platform. IBM, in association with COVENTOR, has successfully implemented a 3D Virtual Fabrication methodology to rapidly improve the yield of high performance 22nm SOI CMOS technology.
The CTO-Semiconductor of COVENTOR, Dr. David M. Fried was in attendance while IBM’s Ben Cipriany presented an interesting paper on this work at The International Conference on Simulation of Semiconductor Processes and Devices (SISPAD 2013). The paper is available at the link “IBM, Coventor present 22nm Virtual Fabrication Success at SISPAD” at the COVENTOR website.