Press Coverage

Rapid Yield Optimization at 22nm Through Virtual Fab
by Pawan Fangaria

Remember? During DAC 2013 I talked about a new kind of innovation: A Virtual Fabrication Platform, SEMulator3D, developed by COVENTOR. Now, to my pleasant surprise, there is something to report on the proven results from this platform. IBM, in association with COVENTOR, has successfully implemented a 3D Virtual Fabrication methodology to rapidly improve the yield of high performance 22nm SOI CMOS technology.

The CTO-Semiconductor of COVENTOR, Dr. David M. Fried was in attendance while IBM’s Ben Cipriany presented an interesting paper on this work at The International Conference on Simulation of Semiconductor Processes and Devices (SISPAD 2013). The paper is available at the link “IBM, Coventor present 22nm Virtual Fabrication Success at SISPAD” at the COVENTOR website.

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Coventor launches ‘Virtual fabrication’ software

Micro Manufacturing

Coventor Inc., a supplier of virtual fabrication solutions for semiconductor devices and micro-electromechanical systems (MEMS), announced the availability of its SEMulator3D 2013 “virtual fabrication” software platform.

SEMulator3D 2013 offers physical accuracy and predictive modeling capabilities to process development and integration, according to the company. The software makes “virtual fabrication” available to the broader semiconductor ecosystem, helping reduce silicon learning cycles and the billions of dollars spent reaching manufacturing readiness, the Cary, N.C.-based company reports.

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Conventor’s CTO Dr. David Fried to Discuss 3D Virtual Fabrication Break Through at Semicon West 2013 Conference

EE Journal

CARY, North Carolina – June 26, 2013 – Coventor®, Inc., the leading supplier of virtual fabrication solutions for semiconductor devices and micro-electromechanical systems (MEMS), will participate in SEMICON West 2013 in San Francisco, CA from July 9 to July 11, 2013 with a featured technical presentation by Coventor’s CTO Dr. David Fried and live software demonstrations that showcase the latest ‘virtual fabrication’ innovations aimed at significantly reducing the silicon learning cycles and billions of dollars spent reaching manufacturing readiness for integrated 3D processes.

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New Process Modeling Mechanism

by Bryon Moyer
EE Journal

Simulation is all about using the simplest possible modeling technique that gives enough accuracy to make the results useful. Simplicity typically speeds up simulation – and, in many cases, makes the problem tractable in the first place.

But at some point, the unnecessary details that the modeling abstractions hide become necessary. At that stage, if you’re lucky, you can tweak your modeling technique to allow for the now-important effects. But eventually you may to have to take a new approach.

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Physical process simulation

Brian Bailey
5/28/2013 7:34 PM EDT

One of things I have learned is that you cannot understand everything associated with designing and making of semiconductors. The physics associated with the manufacturing process, while highly interesting, involves a lot more material science than I care to learn. But for others this is the core of their business and I learned a lot more about it when I spoke to David Fried, the CTO of Coventor.

Now, while I cannot understand many of the details behind their product, the rational for it is blazingly clear. Let me start in the land of functional verification. We do simulation for a number of reasons. The first is that it is too expensive to try something out in silicon before you have a reasonable confidence that it will work. The second is that once you have created the device, you have limited visibility into what is going on inside the chip. So, simulation serves both purposes. First you can ensure that you only go to silicon when you are confident enough that it will work and secondarily, the simulation provides you much more visibility into what is happening so that debug is a lot simpler.

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Fabless, IP designers need process simulation tools, says Coventor CTO

By Luke Collins

Early adopters of advanced process technologies need to be able to model process variability for themselves, so they can understand how it is likely to impact their designs, according to David Fried, CTO of process simulation company Coventor.

“Too many early users of these processes have been burned by thinking that if a design is DRC-clean they will get what they want,” he said. With fabless companies, especially in the mobile sector, under pressure to start designing with new processes before they have been finalised, insights into the impact of process variability could enable defensive design techniques that would mitigate the effects of process variability issues.

Fried sees a number of uses for process modelling in this context. For example, a team working on a fast SERDES in an evolving process might need to know how the different ways in which the process could evolve would affect their design’s performance and noise margins. Physical IP vendors might want to understand how the evolution of process parameter distributions over time would impact their offerings. And manufacturing specialists could use the approach to analyse the way in which one layer influences the printability of another.

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SEMulator3D – A Virtual Fab Platform

byPawan Fangaria
Published on 05-30-2013 06:30 PM

Yes, it’s a pleasant surprise; it is Virtual Fabrication Platform, one of the new innovations in 2013. I was looking around for what kind of breakthrough technologies will be announced in DAC this year. And here I came across this new kind of innovative tool which can produce final virtual fabricated 3D structures after following all the complex steps of actual fabrication process based on process parameters and design data. Amazing, isn’t it?

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Virtual Fabrication Allows Process Development to Keep Pace

GSA Forum
David Fried, CTO, Coventor, Inc.

It is difficult to imagine what the world of IC design would be like without tools that allow engineers to model, simulate, optimize and “virtually” replicate the millions of gates and transistors that comprise a modern chip. Indeed, it would be literally impossible to design these types of devices without sophisticated automation tools, higher-level abstraction methodologies and extremely accurate simulation, modeling and checking technologies.

To manage ever-increasing complexity, the electronic design automation (EDA) infrastructure has evolved into a highly organized hierarchy. At the lowest level of abstraction, compact models and SPICE serve circuit designers with analytical tools to design small circuits with high precision. At higher levels of abstraction, VHDL, Verilog and synthesis tools allow larger more complex designs to be assembled in virtual space. Routing tools allow massive monolithic products to be wired and analyzed virtually, while essentially ignoring the details of lower levels of this hierarchy. With this advanced EDA infrastructure in place, the design community is now creating massive multi-core processors with embedded memories and advanced I/O capabilities.

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