One of the highlight events every year on the MEMS calendar is the IEEE International Conference on MEMS. This is a prestigious gathering that attracts the true thought leaders in MEMS – from both the commercial and academic sides of our industry. The IEEE describes it, quite rightly, as the “flagship annual event of the MEMS community.”
The event organizers often hold the conference in some pretty exotic places – like Cancun, Mexico; Sorrento, Italy; and Istanbul, Turkey. While those are great destinations, it can be hard for some people to justify the travel to their bosses. read more…
by Pawan Fangaria
The design and manufacture of MEMS is very different and in many ways more complex process than even the most advanced ICs. MEMS involve multiple degrees of freedom (i.e. the device to exhibit different characteristics under different physical state, motion or mechanics), making fabrication of MEMS extremely complex; and hence the processes are highly customized and typically linked to particular design or device. The process flow and design parameters are highly sensitive to each other, thus requiring multiple build-and-test cycles and longer MEMS process learning cycles. And these days most of electronic devices or semiconductor designs involve MEMS integrated into them, necessitating a MEMS+IC design approach. For example, gyroscopes are being used in smartphones in big way to enhance motion detection and orientation. Given the cut-throat competition in the mobile market, with increasing feature sets and shrinking windows of opportunity, it’s critical that process learning cycles for MEMS development move from time-consuming build-and-test methods to more efficient methodologies to streamline the handoff from design to manufacturing.
The good news is that Coventor’s SEMulator3D tool (about which I had earlier talked in the context of Virtual Fabrication Platform for semiconductor design ICs) is providing an excellent platform for virtual modeling of MEMS as well. Physical data (such as capacitance) can be extracted from the model for quantitative analysis and process variation studied to quickly predict the exact model of interest before actual fabrication, thus reducing the learning cycle for MEMS.
From your friends and partners at Coventor around the world, we wish you best wishes for a safe and happy holiday season, and a prosperous New Year.
As always, we are standing by to help you get through any of your end-of-year design needs. Our support personnel are available through the coming week, with the exception of Wednesday December 25 and Wednesday January 1 when our worldwide offices are closed for the holidays.
As a reminder, here is contact information for Coventor resources
System Requirements, Software Downloads, Customer Portal
Email Technical Assistance:
EAST US: email@example.com
WEST US: firstname.lastname@example.org
We look forward to working with you in 2014 to reach new levels of MEMS and IC design success.
I just got back from the annual International Electron Devices Meeting (IEDM) in Washington, DC. As is customary, a great deal of attention was paid to Front End of Line (FEOL) transistor innovations such as FinFET, FDSOI, Graphene, Nanotubes, Nanowires, etc. However, some of the greatest complexity in semiconductor development and manufacturing these days is in the interconnect, or Back End of Line (BEOL). The BEOL contains some of the finest geometries in the technology, since die area scaling is usually limited by the wiring density. Because wires are being designed at such fine dimensions, their height has been increased to recoup the resistance penalty. This makes the dimensions even more challenging through high aspect ratios. Finally, the BEOL contains some of the most complex and unstable materials due to the desire to reduce capacitance (porous low-K dielectrics), the requirement to minimize thermal cycles (for FEOL stability), and the inherent reliability risks associated with the metals involved. I’ve been a transistor specialist for most of my career, but I have to admit… the BEOL has gotten incredibly difficult.
At the 2013 edition of the IEDM conference held this month in Washington, DC, some of the brightest minds in the design and manufacture of semiconductors gathered to discuss trends and challenges in the IC industry. One particular session, hosted by Coventor, assembled 5 experts on leading edge process development from some of the biggest chip players in the business: IBM, GlobalFoundries, Samsung, ST Microelectronics and renowned research organization IMEC.
Coventor CTO David Fried leads a panel of industry experts on a discussion of how to address challenges to continued IC scaling
The consensus of this elite group was not surprising: there is no shortage of new and unprecedented challenges standing in the way of continued scaling of IC technology. Each panelist offered their own opinion on what the biggest challenge is, and they ran the gamut of tough tasks.
By Richard Goering on December 11, 2013
Micro-electrical mechanical systems (MEMS) have been a niche technology for many years, but a new generation of MEMS ICs is emerging, according to Mike Jamiolkowski, CEO of Cadence partner and MEMS tool provider Coventor. Barriers to the use of MEMS technology, such as the need for PhD-level experts and non-reusable foundry processes, are starting to ease.
In this interview Jamiolkowski talks about new trends in the MEMS market, discusses his company’s MEMS+ tools and how they work with the Cadence Virtuoso platform, and notes a new MEMS+ capability to output reduced order models in the Verilog-A language.