Coventor Blog

Challenges in 3D NAND Flash Processing

With 2D planar NAND flash hitting scaling issues at sub-20nm technology nodes, 3D NAND flash has become all the rage. Instead of restricting memory cells to a single plane and scaling the devices horizontally, memory cells can also be stacked vertically, allowing high cell density while side-stepping scaling issues (for now). Major NAND flash manufacturers have each developed their own designs and technology for 3D NAND flash, and with the addition of vertical cell stacking, new issues in 3D process integration arise.

For instance, in Samsung’s Terabit Cell Array Transistor (TCAT) technology [1], a memory cell array is formed of NAND flash strings with vertically-oriented channels and word lines arranged in planes. Of particular interest is the gate integration scheme: TCAT uses charge-trapping (SONOS/TANOS) with metal replacement gates, the combination which is expected to result in faster erase speed, wider threshold voltage margins, etc. The cell gates are created using a sacrificial nitride layer combined with a damascene process: the entire stack of SiO2/SiN layers is etched (“word line cut”) after staircase formation, then nitride is removed through wet etching with hot phosphoric acid, leaving behind gaps separated by the oxide. These gaps are then filled with dielectric and gate metal to create gate-all-around structures.
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Sneak Peak: New Capabilities for Micro Scanning and Projection Mirrors

By Gunar Lorenz, Director, System Level Simulation

Once again we are entering the final phase of a MEMS+ release cycle. We are tying up loose endsfor for another exciting release, over the summer, of our unique MEMS design software. I believe that the results of our latest research and development efforts will impress our users. You may ask: what’s so exiting about the new release? Well, it will surely require more than one blog to tell you about the many new features. For this blog, I will focus on the new capabilities in MEMS+ 5.0 that address the special design challenges presented by micro mirrors. Even if you are not working on micro mirror applications yourself, you may have heard about the new mini-projectors for smartphones from Fraunhofer or the new industrial devices from companies like Mirrorcle Technologies, Inc., Hamamatsu or Preciseley Microtechnology Corp: read more…

Are MEMS bolometers the next big thing?

By Steve Breit, Vice President Engineering

I often feel that Coventor is in the crow’s nest for spotting trends in the MEMS industry because our customers use design and simulation software early in the product development cycle to evaluate and optimize new concepts. Through evaluation and support requests from our worldwide customer base, we get some visibility on the types of MEMS our customers are working on. We’re obligated, of course, to keep the details of customer requests confidential. But, when multiple customers start asking questions about a particular type of MEMS that previously hasn’t seen much activity, we begin to suspect a new trend is developing. Such is the case for MEMS bolometers, or microbolometers. read more…

SEMulator3D 2014: Why this is big news

by David M. Fried

We’re right on the cusp of the SEMulator3D 2014 release. This has been a big release in the making, and I know I’m not alone in my excitement as we approach release day. You can read the press release and get an updated data sheet, but I wanted to take the opportunity to give you my personal engineer-to-engineer perspective on why this is so exciting to anyone doing advanced process development. read more…

Some Thoughts on 3D Integration and How to Better Understand its Complexity

As semiconductor technology scales into the 20nm node and beyond, the process complexity, electrical performance and circuit density tradeoff becomes extremely difficult to optimize. As the demand for increased density, lower power, and higher bandwidth accelerates, the motivation for 3D integration becomes more attractive. With the advent of 3D integration comes the promise of “beyond Moore’s law” integration by stacking chip-on-chip and connecting them with through-silicon-vias (TSVs). Numerous definitions of 3D integration exist, for example multi-die packages (also known as system-in-package, or SiP) in which multiple die are mounted on a common substrate that connects them, package-in-package (PiP) where a number of SiPs are mounted in a larger SiP, and package-on-package (PoP) where one SiP is mounted on top of another SiP. All of these approaches offer some degree of density advantage, however, the ultimate objective of 3D integration is the multiple stacking of silicon levels on top of one another, each of which contain subsequent levels of circuitry, all connected with TSVs. This approach to 3D integration has been demonstrated by CEA-Leti and reported in IEEE Spectrum (see Figure 1 below). read more…

3D printed model of FinFET attracts attention at SPIE Conference

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3D printing has become all the rage in many areas, from home hobbyists to high-end industrial applications. The convenience, flexibility, functionality and decreasing price for printing things in 3D makes it an appealing tool for a wide range of purposes. So we thought we’d put it to use for demonstrating how virtual fabrication can help engineers understand the technical nuances of advanced process technologies – as well as show off a cool feature of our SEMulator3D tool. read more…