Posted in: Coventor Blog by Marketing | Comments Off on CMOS Image Sensors (CIS): Past, Present & FutureWednesday, June 14, 2017
By: Sofiane Guissi, Semiconductor Process & Integration Engineer, Coventor
Over the last decade, CMOS Image Sensor (CIS) technology has made impressive progress. Image sensor performance has dramatically improved over the years, and CIS technology has enjoyed great commercial success since the introduction of mobile phones using on-board cameras. Many people, including scientists and marketing specialists, predicted 15 years earlier that CMOS image sensors were going to completely displace CCD imaging devices, in the same way that CCD devices displaced video capture tubes during the mid-1980’s. Although CMOS has a strong position in imaging today, it has not totally displaced CCD devices. On the other hand, the drive into CMOS technology has drastically increased the overall imaging market. CMOS image sensors have not only created new product applications, but have also boosted the performance of CCD imaging devices as well. In this paper, we describe the state-of-the-art in CMOS image sensor technology and discuss future perspectives.
By: Michael Hargrove, Semiconductor Process & Integration Engineer
Until EUV lithography becomes a reality, multiple patterning technologies such as triple litho-etch (LELELE), self-aligned double patterning (SADP), and self-aligned quadruple patterning (SAQP) are being used to meet the stringent patterning demands of advanced back-end-of-line (BEOL) technologies. For the 7nm technology node, patterning requirements include a metal pitch of 40nm or less. This narrow pitch requirement forces the use of spacer based pitch multiplication techniques. Unfortunately, these techniques have high process/lithography variability, which can severely impact RC and overall device performance.
Posted in: Coventor Blog by Sandra Liu | Comments Off on Photoresist shape in 3D: Understanding how small variations in photoresist shape significantly impact multi-patterning yieldWednesday, April 12, 2017
By: Mustafa B. Akbulut, Ph.D., Team Lead, Quality Assurance, Semiconductor Solutions
Things were easy for integrators when the pattern they had on the mask ended up being the pattern they wanted on the chip. Multi-patterning schemes such as Self-Aligned Double Patterning (SADP) and Self-Aligned Quadruple Patterning (SAQP) have changed that dramatically. Now, what you have on the mask determines only a part of what you will get at the end. read more…
Posted in: Coventor Blog by Marketing | Comments Off on Semiconductor Process Development: Finding a Faster Way to ProfitabilityThursday, February 16, 2017
By: Katherine Gambino, Strategic Accounts Manager
Building a chip fabrication facility requires billions of dollars in investment for land, buildings, processing equipment, chemical and hazardous material safety, not to mention the deployment of hundreds of highly experienced process engineering and manufacturing personnel. Bringing up an advanced semiconductor process in any fab, new or established, is a several-hundred-million dollar effort, typically requiring two or more years of experimentation with process equipment and process recipes, led by engineers with years of process integration and chip manufacturing expertise.
Posted in: Coventor Blog by Marketing | Comments Off on The Value of Integrating Process Models with TCAD Simulation (and some tips on how to do it)Friday, January 20, 2017
By: Shi Hao (Jacky) Huang, PhD, Semiconductor Process & Integration Engineer
Nowadays, novel semiconductor technologies have brought complex process flows to the fab. These process flows are needed to support the manufacturing of advanced 3D semiconductor structures. It can be helpful to model process flows, and their effect on a novel device, prior to physical fabrication.
Posted in: Coventor Blog by Marketing | Comments Off on BEOL Barricades: Navigating Future Yield, Reliability and Cost ChallengesThursday, December 15, 2016
By: David Fried, Ph.D., Chief Technology Officer, Semiconductor
Coventor recently assembled an expert panel at IEDM 2016, to discuss changes to BEOL process technology that would be needed to continue dimensional scaling to 7 nm and lower. We asked our panelists questions such as: read more…