Coventor Blog

Lithography challenges threaten the cost benefits of IC scaling

By David Fried
Tech Design Forum

Will we be able to engineer another technology node that brings the usual cost and area savings without EUV lithography? I have serious doubts.

EUV lithography was supposed to be ready for the 45nm process node, and was then delayed until 32nm and later, 22nm. Today, major semiconductor companies are continuing to develop their offerings. Some will use the upcoming IEDM to detail their 1xnm processes, developed despite the lack of EUV’s patterning capabilities.

Why the delay with EUV? The story has been told many times: a combination of complex electro-optics, problems with the power of the illumination source, resist sensitivity and defectivity. The list of EUV challenges is long, but the summary is short: it’s not ready yet!
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MEMS Coming of Age

By Tom Flynn

NAPA, California – It’s always difficult to know exactly where you are at any given moment in a dynamic industry like MEMS. While our meetings with MEM designers who are building the next generation of devices gives us at Coventor a unique perspective, it’s just one point of view. It’s critical we see many views of the industry and that’s why the MEMS Executive Congress, an annual event put on by the MEMS Industry Group (MIG) is something we look forward to every year.

This year the MEC was held in Napa. It seems appropriate because, like a fine wine, MEMS is coming of age. Presentations from people with perspectives from around the entire ecosystem of MEMS confirmed that, and the record number of attendees all were left with a sense of excitement about the future of MEMS.


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Semiconductor Fabrication Module Optimization

by Pawan Fangaria
SemiWiki

The growing process integration complexity at each technology node has increased development time and cost, and this trend looks to continue. There is a looming risk of delivering unrepeatable critical unit processes (or process modules) that would require revisiting development and manufacturing requalification or in severe cases a design re-spin. Below the 22nm process node, tremendous effort is necessary to meet process integration specifications with a yielding process that is robust in the face of unavoidable manufacturing variation. read more…

MEMS+ 4.0: Removing the Barrier between MEMS and ASIC designers

By Steve Breit, V.P. Engineering
MEMS sensors never stand on their own – there’s always an accompanying ASIC that conditions the MEMS output or controls the MEMS. We’ve written frequently in past blogs and white papers about the barrier between MEMS and ASIC design teams. For purposes of functional verification, the ASIC designers need a MEMS block on their schematics, with an underlying model that captures the behavior of the MEMS. The problem arises because the MEMS and ASIC design teams use fundamentally different approaches to simulate the functioning of their respective designs. The MEMS designers use finite element analysis tools while the ASIC designers use analog/mixed-signal circuit simulators such as Cadence Spectre. There’s simply no way to include a conventional finite element model in a circuit simulator, and even if there was the simulations would run so slowly that it would have no practical use. To overcome this incompatibility, all MEMS companies that we’ve engaged with rely on handcrafting models of their MEMS devices in a hardware description language like Verilog-A that is compatible with the ASIC team’s circuit simulator. It takes lots of time, specialized knowledge, and skills to handcraft and verify a MEMS device model in Verilog-A. Because of the technical difficulty, handcrafted models are typically overly simplified, omitting important aspects of the MEMS behavior such as cross coupling between mechanical modes and non-linear effects. Moreover, an ongoing effort is needed to keep the handcrafted models in sync with the actual MEMS design, leaving plenty of opportunities for version skew and human error. The end result, undoubtedly, is extra design spins that are costly not only in engineering time, but in longer time to market. The graphic below illustrates this barrier.
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MEMS Executive Congress: Focus on Mobile

The MEMS Executive Congress (November 7-8 in Napa, Calif.) is a great annual event that brings together important stakeholders from throughout the MEMS ecosystem – MEMS developers, foundries, developers of MEMS-enabled products and design tool companies such as Coventor. We look forward every year to hear about important trends, technology developments and new applications areas – and, of course, meet up with long-time friends within the industry.

It’s no surprise that this year’s event is focused on mobile as mobile devices are driving growth and opportunity in the MEMS industry. Smart phones, tablets, games, and cameras are all increasing their MEMS content with a broad array of new capabilities that enable users to interact with their environment. Add in the growing trend for wearable computing – for health, sports, education and entertainment applications – and mobile products are clearly the key focal point for MEMS. As one observer pointed out, “mobile devices are quickly becoming the planet’s foremost wireless sensor network.” read more…

Virtual Fabrication: Not just for ICs. Better insight into manufacturing helps MEMS designers, too.

With the current focus on IC processing challenges at sub-20nm device length scales, interest in micron-scale wafer processing seems to be out of the limelight. However, in the world of MEMS, micron-scale processing is dominant for high-volume components such as gyroscopes and accelerometers. In a typical MEMS process flow, tens of microns of silicon are etched to release structural features that are a few microns wide. And while those in IC process integration may think that MEMS processing should be simpler than for leading-edge ICs, the increasing complexity and customization in MEMS designs raise a different set of processing issues, which demand further understanding for successful device manufacturing. read more…