David Fried, CTO, Coventor, Inc.
It is difficult to imagine what the world of IC design would be like without tools that allow engineers to model, simulate, optimize and “virtually” replicate the millions of gates and transistors that comprise a modern chip. Indeed, it would be literally impossible to design these types of devices without sophisticated automation tools, higher-level abstraction methodologies and extremely accurate simulation, modeling and checking technologies.
To manage ever-increasing complexity, the electronic design automation (EDA) infrastructure has evolved into a highly organized hierarchy. At the lowest level of abstraction, compact models and SPICE serve circuit designers with analytical tools to design small circuits with high precision. At higher levels of abstraction, VHDL, Verilog and synthesis tools allow larger more complex designs to be assembled in virtual space. Routing tools allow massive monolithic products to be wired and analyzed virtually, while essentially ignoring the details of lower levels of this hierarchy. With this advanced EDA infrastructure in place, the design community is now creating massive multi-core processors with embedded memories and advanced I/O capabilities.
MEMS+ 3.0 software platform delivers new fluidic, package and noise simulation capabilities; an expanded component library; and performance enhancements
CARY, North Carolina – February 4, 2013 – Coventor®, Inc., the leading supplier of design automation software for developing micro-electromechanical systems (MEMS), today announced immediate availability of its new MEMS+® 3.0 design platform that accelerates development of complex 3D systems with state-of-the-art actuators, accelerometers and gyroscopes, microphones and other types of MEMS devices.
Coventor and its SEMulator 3D product was featured EE Times
Coventor and its SEMulator 3D product was featured as one of the ten technologies that will change the world in 2013, according to EE Times.
Electronic Engineering Journal
by Bryon Moyer
“I need a brush.”
What would you do given such instruction by someone to whom the response, “Can you be more specific, please?” would be considered inappropriate? It’s a hard request (or demand) to satisfy if you know absolutely nothing about his or her intent. It’s almost as bad as the “Bring me a rock” theory of management, except that that’s simply a way of ensuring that your employees are never quite sure if they’re doing the right thing, and so they remain nervous and stressed; putty in your hands. No, in this case, we’re just assuming poor communication skills, nothing Machiavellian.
Electronic Engineering Journal
by Amelia Dalton
MEMS is everywhere. From your smartphone to your television to that gesture controlled game system that I didn’t get for Christmas. In honor of the Consumer Electronics Show taking place in Las Vegas next week, we’re talking about innovation in the MEMS marketplace. This week my first guests are Alissa Fitzgerald (AMFitzgerald) and Peter Himes (Silex). We’re gonna get down to brass tacks about MEMS and how you can get your next MEMS design up and running. Keeping with the MEMS theme, my second guest this week is Tom Flynn (Coventor). Tom and I talk about the tricky dance of EDA tools for MEMS designs. It’s complicated, but Tom will show you the steps.
Coventor’s Director of European Operations Gerold Schröpfer was recently interviewed on the topic of energy harvesting for a newsletter produced by the European Metrology Research Programme.
What does Coventor do?
Coventor develops and supplies software tools that can be used for the design of micro electromechanical systems (MEMS) and the modelling of semiconductor and MEMS manufacturing processes. The modelling of MEMS energy harvesters is a small but growing area of our business.
Our products enable the co-design and co-simulation of a harvesting device and a conditioning circuit together. It allows users to play around with the both the harvester design parameters and circuit parameters in order to optimise device performance before committing to time-consuming and costly build-and-test cycles. The design can also be checked for high stress areas that may lead to breakage when the device is overloaded.