By Mark LaPedus
The shift from planar devices to finFETs enables chipmakers to scale their processes and devices from 16nm/14nm and beyond, but the industry faces several challenges at each node.
Cost and technical issues are the obvious challenges. In addition, cycle time—a key but less publicized part of the chip-scaling equation—also is increasing at every turn, creating more angst for chipmakers and customers alike. In fact, cost, technical hurdles and cycle time are all contributing to the ongoing slowdown of Moore’s Law.
Cycle time is the amount of time it takes to process a wafer lot in a fab from start to finish. Typically, a wafer lot consists of 25 wafers, which move through various process steps in a fab. An advanced logic process could have from 600 to 1,000 steps or more.
A simple way to look at cycle time is to apply a probability theory called Little’s Law in the fab. In this case, cycle time equals work-in-process (WIP) over the start rate, according to KLA-Tencor. For example, if a fab has 12,000 lots, and it processes 4,000 lots per month, the total cycle time is 3 months, according to KLA-Tencor.