By Mark Lapedus
Chipmakers are ramping up their 14nm finFET processes, with 10nm and 7nm slated to ship possibly later this year or next.
At 10nm and beyond, IC vendors are determined to scale the two main parts of the finFET structure—the transistor and interconnects. Generally, transistor scaling will remain challenging at advanced nodes. And on top of that, the interconnects may continue to fall further behind the curve.
In fact, the interconnect issues began to emerge at 20nm or so, and the problems are becoming worse at each node. Interconnects—the tiny copper wiring schemes in devices—are becoming more compact at each node. This, in turn, is causing a degradation in performance and an increase in the resistance-capacitance (RC) delay in chips.