Tech Design Forum Blog
By Luke Collins

Semiconductor process development lacks tools that offer the same kind of support for hierarchy and abstraction that have enabled chip designers to handle the vast increase in capacity of modern processes, according to David Fried, CTO of Coventor, which provides the Semulator 3D software used to produce our finFET tipsheet.

Speaking at a reception at IEDM in San Francisco this week, Fried argued that there is a mismatch between the cost of building a fab and establishing a new process in it and the sophistication of the tools used to help develop the processes.

Read more at: http://www.techdesignforums.com/blog/2012/12/12/hierarchy-abstraction-process-development/