Request White Paper:
FinFET Front-End-of-Line (FEOL) Process Integration with SEMulator3D®

Purely geometric scaling of transistors ended around the 90-nanometer (nm) era. Since then, most power/performance and area/cost improvements have come from structural and material innovations. Silicon-on-Insulator (SOI), first “partially depleted” and more recently “fully depleted” as well as embedded stressors, High-K / Metal-Gate (HKMG) and now FinFETs are examples of technology innovations that have been required to continue scaling below 90nm. Virtual fabrication with Coventor’s SEMulator3D 2013 process modeling platform offers capabilities that reduce the time and resources required to develop advanced technologies through predictive design technology modeling, variation analysis and quantitative data extraction. This white paper demonstrates virtual fabrication capabilities through examples in the development of a hypothetical FinFET technology.

Complete the form below to receive a free copy of the white paper.

First Name *
Last Name *
Company or University Name *
Email *
Phone *
City/State *
Country *
What is your primary interest or work: *

If other, list primary work interest here:
Would you like a technical expert from Coventor to contact you about your process modeling needs *

Comments are closed.