SEMulator3D Advanced Modeling

SEMulator3D enables predictive structural modeling of complex process flows. To correctly predict the end result of a complete process flow, each process step must be modeled accurately. The SEMulator3D Advanced Modeling package adds two additional process steps to the standard library: MultiEtch and Selective Epitaxy. These two steps provide more accurate modeling of plasma (dry) etching, and selective epitaxial growth, respectively. Using Coventor’s unique Surface Evolution engine, advanced modeling process steps mimic the physical behavior of etching and epitaxy to achieve accurate prediction of device structure in both nominal and off-center process conditions. Advanced modeling process steps are fully integrated into the SEMulator3D Process Editor and may be used at any point in the process flow where more accurate physical process behavior is required. This enables a combination of fast geometric process modeling and more detailed, physics-driven structural modeling.

MultiEtch

Plasma (dry) etches are critical for both FEOL and BEOL in semiconductor technology due to their flexibility, selectivity and directionality. By varying process parameters, etch engineers can achieve selectivity to specific materials of interest and control lateral etch bias, polymer formation and sputtering rate.

MultiEtch models multi-physics plasma etches on multi-material film stacks. With a relatively simple set of behavioral input parameters, including selectivity, lateral etch bias, taper angle, and sputter rate, MultiEtch is capable of modeling very complex etches. Etch behavior can be specified on a per-material basis to model (for example) mask sputtering as well as taper due to polymer deposition.

Figure 1. M2-V1 process flow after (a) M2-L1 lithography, (b) M2-L2 litho, (c) V1 partial etch, (d) BLok open and (e) CuBS.

As an example, consider the M2-V1 process flow shown in Figure 1. This BEOL via chain integration features a trench-first metal hard mask with a self-aligned via (TFHM-SAV). Achieving a suitable chamfer on V1 is critical to avoid excessive electromigration and device failure. In this example, the chamfer is caused primarily by sputtering during the M2 over-etch (OE). The M2 OE is typically designed to avoid etching BloK, and as a result uses a strongly polymerizing chemistry that necessitates a higher bias voltage. Figure 2 shows the evolution of the M2 OE; note the formation of the chamfer and selectivity to the low-k ILD. Note that although the selectivity is very good, all materials on the wafer are etching and hence the ramifications of excessive over-etch, for example break-through of the TiN hard mask, may be investigated and understood.

Figure 2. Evolution of M2 OE. Note formation of chamfer on V1
and erosion of the TiN hard mask and BloK.

MultiEtch may also be used to model similarly interesting phenomena in STI, fin, gate and spacer etches in the FEOL.

Selective Epitaxy

Selective epitaxial growth (epitaxy) was a key enabler for strained silicon technology in planar devices, and remains essential to achieving FinFET performance goals. Due to complex growth characteristics and limited ability to perform on-wafer metrology, epitaxy can be a significant source of both technology risk and device variation. Modeling can mitigate this risk through improved understanding of both growth characteristics and sources of variation.

SEMulator3D models epitaxy through characterization of the growth rates on the major silicon plane families. The structures achieved through epitaxy are typically strongly influenced by the slow-growingfamily of planes. Epitaxial behavior at interfaces with non-crystalline neighbor materials can also be important, and may be controlled in SEMulator3D through material-specific overgrowth parameters. Using this relatively small set of parameters, the physics-driven surface evolution modeling engine is able to model very dynamic, complex epitaxial growth characteristics.

Consider the example sub-22nm FinFET technology shown in Figure 3. This example technology uses spacer patterning for fin definition, embedded epitaxial source-drains (PFET only), differential replacement HKMG integration and self-aligned local interconnects.

Figure 3. 0.074 um2 SRAM cell in example process flow (a) Fin Definition and STI, (b) sacrificial gate module, (c) spacers and embedded SiGe, (d) Replacement Metal Gate and (e) Middle of Line modules

Figure 4 shows the evolution of epitaxy on a single fin. In this orientation, with fin sidewalls aligned withdirections, the epitaxial growth is limited by slow-growingplanes. The overgrowth characteristics on neighboring non-crystalline materials have a significant effect on the final dimensions of the epitaxial growth, as does theplane growth rate.

Figure 4. Evolution of epitaxial growth (a) under nominal process conditions, (b) with overgrowth on neighboring non-crystalline materials (popped), (c) with fastergrowth rate.

Crystal Etch

In CMOS source/drain engineering, recessing before selective epitaxial growth can contribute to channel strain and reduce short channel effects. One recessing method uses crystallographic or anisotropic etching with wet chemistries (such as TMAH or NH4OH) to expose {111} planes in crystalline silicon, creating sigma-shaped cavities in which epitaxy is grown.

The Crystal Etch process models crystallographic etching through the use of different etch rates for major silicon plane families. Fast and slow etch planes can be specified to adjust for different etching chemistries, and realistic CMOS source/drain profiles can be achieved when this feature is used in conjunction with the Selective Epitaxy process model.

AM-crystaletchvia
AM-crystaletchSD

(1) SEMulator3D model of hydroxide-based etch results in exposed {111} facets. (2) Evolution of CMOS source/drain etch recess.

Pattern Dependent Etching

On-wafer etching behavior is affected by variations in feature size and pattern density. As critical dimension continues to shrink, pattern-dependent etch effects become more pronounced. Features in isolation can etch at different rates than features in densely-patterned areas. Loading effects and varying aspect ratios also result in non-uniform etch profile depths or anisotropy across the wafer. SEMulator3D integrates this pattern dependence with standard etch and Multi Etch modules to model effects such as etch loading, RIE lag, or ARDE.

(3) SEMulator3D model cross-section of etch profile and depth pattern dependence for varying line width and pitch.

(3) SEMulator3D model cross-section of etch profile and depth pattern dependence for varying line width and pitch.

Conclusion

The SEMulator3D Advanced Modeling package is a powerful, predictive modeling tool to build process understanding, mitigate technology risk and eliminate cycles of learning in technology development. With minimal input parameters that are easy to calibrate, process engineers can gain significant understanding of the behavior and variability of etch and epitaxy steps and their ramifications in the context of the full technology flow.

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