Semiconductor Process Development/Integration

Ed Korczynski, Sr. Technical Editor at PennWell

Accelerating demand for faster, smaller, more power efficient circuits continues to drive the Semiconductor industry towards new technology nodes. New materials and processing techniques such as Copper metal lines, high-K dielectrics, metal replacement gates and strained Silicon technology must be used to achieve ever-smaller device sizes and to improve transistor performance. Furthermore, test wafers are more expensive due to increasing mask costs, material costs and wafer size.

SEMulator3D can reduce process integration costs through process visualization. Identifying problems in a virtual 3D environment saves WIP turns and reduces overall process integration time. 

SEMulator3D bridges the gap between simple analytical models and TCAD simulations, providing detailed insight into an entire process flow from FEOL to BEOL to packaging.

• Visualize and analyze important process details, such as divot formation and spacer undercut.
• Verify correct gate/channel configuration.
• Verify correct electrical connectivity.
• Build and view test macros before fabrication.
• Understand and verify Failure Analysis results.
• Demonstrate desired geometry to unit process engineers in 3D.
• Formulate and document design rules.

Cross section view through a 3D model of three 6T-SRAM cells