25nm NAND Flash Technology
Download 25nm NAND Flash Technology SEMulator3D Reader model
File size 11.9 MB
Please save this file to your local disk. You must install SEMulator3D Reader to view this file
IMFT (a partnership of Intel and Micron) announced the availability of the world’s first 25nm NAND flash technology in early 2010 (Ref. 1). At the time, the 25nm process was not only the smallest NAND technology in the world, it was the smallest semiconductor technology of any type. The fabrication of 25nm gates was remarkable considering the 193nm light source wavelength in state-of-the-art immersion lithography. SEM images of the technology were published in EE Times and other news media. One of these images (Ref. 2 and 3), showing a word-line cross section of the NAND flash gates, is reproduced below:
Figure 1
A paper presented at IEDM 2010 by authors affiliated with Samsung provides similar images of their 27 nm NAND flash technology (Ref. 4).
This example shows how the fabrication process for 25nm NAND flash can be modeled in SEMulator3D using standard lithography, deposit, and etch steps. The fabrication process relies on two sequences of self-aligned double patterning (SADP) to achieve a feature density in both the bit-line and word-line directions that is as much as double the density that would be possible with lithography-based patterning alone. By employing self-alignment, both in the actual process and in modeling the process in SEMulator3D, only two masks are required for the portion of the fabrication sequence shown in this example.
Figure 2
The process starts with depositing tunnel oxide (black) and floating gate poly on the wafer. Then photo resist (red) is spun on and patterned with immersion lithography (exposed resist is dark red). The sequence of images above starts at this point, showing the SADP sequence that is used to create the bit lines. After removing the photo resist (second image), a nitride layer is deposited on the wafer (third image). The thickness of the nitride layer must be carefully controlled to assure uniform width and spacing of the bit lines. The nitride layer is dry etched to expose the floating gate poly and trapped resist (fourth image). The resist is ashed away, leaving a nitride hard mask for the bit lines (fifth image). Note that this SADP sequence has achieved a line density that is double that of the initial lithographic pattern. A subsequent sequence of etch steps (sixth image) removes the unprotected floating gate poly, tunnel oxide, and creates the isolation trenches. The emulation of the isolation trench etch in the silicon substrate makes use of the ability an arbitrary sidewall profile in SEMulator3D etch steps.
Figure 3
Subsequently, the nitride hard mask is removed, the isolation trenches are filled, and a sequence of deposit steps adds isolation layers, control-gate poly, and tungsten salicide to the layer stack. Then a second SADP sequence, shown in the sequence of images below, is performed to define the word lines.
The animation below shows the fabrication sequence through the formation of the word lines.
Figure 4
The 3D models shown here were created by Coventor based on publicly published information about the IMFT 25nm NAND flash process and similar processes. No proprietary information was used to create these models or images.
References
- Intel News Release, “Intel, Micron Introduce 25-Nanometer NAND – The Smallest, Most Advanced Process Technology in the Semiconductor Industry”, http://www.intel.com/pressroom/archive/releases/2010/20100201comp.htm, Feb. 1 2010.
- Ramesh Kuchibhatla, “IMFT 25-nm MLC NAND: technology scaling barriers broken”, EE Times, http://www.eetimes.com/electronics-news/4088140/IMFT-25-nm-MLC-NAND–technology-scaling-barriers-broken?pageNumber=1, March 22, 2010.
- Andrew Woodward, “IMFT 25 nm NAND Flash: Seeing Double (Patterning)”, SemiSerious blog,
http://www.semiconductorblog.com/2010/03/08/imft-25nm-nand-flash-seeing-double-patterning/ (no longer available on line), March 10, 2010. - Choong-Ho Lee, et al, “A Highly Manufacturable Integration Technology for 27nm 2 and 3bit/cell NAND Flash Memory”, Proceedings of IEDM 2010, December 2010.
