Download 32nm FinFET SRAM Device SEMulator3D Reader model, file size 24.5 MB
Please save this file to your local disk. You must install SEMulator3D Reader to view this file

A highly scaled 32nm FinFet transistor design was presented by a collaboration between Toshiba, IBM, Freescale and AMD at the IEDM meeting in 2008. FinFETs are under consideration for advanced technology nodes due to potential performance and variability advantages over planar FET devices. The device presented and modeled here is an 8-transistor SRAM cell design using FinFET transistors and fabricated on silicon-on-insulator (SOI) wafers.

Figure 1: SEM images of 32nm FinFET

After initial threshold voltage implants, the next steps in the process sequence form the silicon fins by etching through the epitaxial silicon layer on the SOI wafer. An oxide hardmask is used to pattern the silicon. The etch process creates vertical sidewalls on the silicon, but also erodes the oxide hardmask and the buried insulator layer. With SEMulator3D, it is possible to create either a simpler idealized model or a detailed model capturing the over-etch and rounding seen in the SEM images.

Figure 2: FinFet device after fin formation. SEMulator3D can model deposits and etches in a range of detail controlled by the user depending on modeling goals. Top right shows a simple fin structure, bottom right shows the result of more detailed etch modeling, including erosion of the oxide hardmask and over-etch into the buried oxide.

The first Nitride spacer is used during extension implants and defines the channel length. The spacer etch-back is crucial in this process flow as the spacer must be removed completely from the sides of the silicon fins, but must remain on the sides of the gate stack (to mask the polysilicon during subsequent epitaxy). The spacer etch is using a carefully tuned over-etch that accomplishes these goals, but likely also reduces the height of the Nitride hardmask.

Figure 4: Deposit (left) and etch-back (right) of the first spacer. Note the reduction in height of the hardmask (green); the etch must be carefully tuned to remove the spacer from the fins without exposing the gate poly.

The extension implant is performed using an angled implant and a special two-mask scheme to ensure that each fin only receives implants from one side. This reduces variability between devices. For this SRAM device, the scheme requires two masks for nMOS extension implants and one mask for pMOS extension implants that can be easily modeled with SEMulator3D.

Figure 5: Animation showing the single-sided extension implant scheme

The extension implants are followed by an epitaxy step to enlarge the silicon fins in contact areas. High-dose source and drain implants are implemented using a second spacer, and a NiPt salicide is grown on contact areas. Note that the second spacer etch is tuned to expose the top of the polysilicon gate conductor for salicide formation and later contact.

Figure 6: FinFet after S/D implants and silicidation

Contacts are created using a standard dual damascene process. Similar to the fin shapes, SEMulator3D is able to capture metallization in several levels of detail.

Figure 7: After ILD0 deposit and CMP with dual damascene copper contacts.

References
H. Kawasaki et al, “Demonstration of Highly Scaled FinFET SRAM Cells with High-k/Metal Gate and Investigation of Characteristic Variability for the 32 nm node and beyond”, Proc. IEDM 2008, pp. 1-4.