7 nm

What drives SADP BEOL variability?

By: Michael Hargrove, Semiconductor Process & Integration Engineer

Until EUV lithography becomes a reality, multiple patterning technologies such as triple litho-etch (LELELE), self-aligned double patterning (SADP), and self-aligned quadruple patterning (SAQP) are being used to meet the stringent patterning demands of advanced back-end-of-line (BEOL) technologies.  For the 7nm technology node, patterning requirements include a metal pitch of 40nm or less. This narrow pitch requirement forces the use of spacer based pitch multiplication techniques. Unfortunately, these techniques have high process/lithography variability, which can severely impact RC and overall device performance.

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Coventor Unveils New Scientific Findings on Lithography Processing For Improved Semiconductor Scalability and Performance

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At SPIE Advanced Lithography 2017, Coventor Will Present Results of Studies to Increase Density and Yield of Next-Generation Semiconductor Devices

CARY, NC– February 13, 2017 – Coventor®, Inc., the leading supplier of virtual fabrication solutions for semiconductor devices and micro-electromechanical systems (MEMS), will present findings from its research on advanced semiconductor fabrication processes at SPIE Advanced Lithography 2017. The results of these studies provide insight into techniques for advancing the state-of-the-art in semiconductor technology through use of new and emerging photomask, lithography and process technologies. read more…

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BEOL Barricades: Navigating Future Yield, Reliability and Cost Challenges

By: David Fried, Ph.D., Chief Technology Officer, Semiconductor

Figure 1. M2-V1 process flow after (a) M2-L1 lithography, (b) M2-L2 litho, (c) V1 partial etch, (d) BLok open and (e) CuBS.

Coventor recently assembled an expert panel at IEDM 2016, to discuss changes to BEOL process technology that would be needed to continue dimensional scaling to 7 nm and lower. We asked our panelists questions such as: read more…

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IMEC Partner Technical Week Review

IMEC Partner Technical Week Review

By:   Aurélie Juncker, Semiconductor Process & Integration Engineer

a.Fully aligned Via with Cu recess approach - Gayle Murdoch, b. STT-RAM - Davide Crotti, c. N10 Supernova2 process - Matt Gallagher

a. Fully aligned Via with Cu recess approach – Gayle Murdoch, b. STT-RAM – Davide Crotti, c. N10 Supernova2 process – Matt Gallagher

In March 2016, Coventor was invited to the biannual Partner Technical Week (PTW) at IMEC in Leuven, Belgium. IMEC, a world-leading research group in nanotechnology, organizes their Partner Technical Week every 6 months to present scientific results to their partners. During this week, a number of specialists from IMEC’s many partner companies also discuss their progress in areas related to IMEC’s research. This event brings together a large number of engineers who are specialists in their domain, and provides an interesting forum to leverage the scientific knowledge gained by IMEC and its partners. read more…

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Asymmetric variability issues could impact 7nm processes

By Luke Collins, Tech Design Forum

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New variability issues highlighted by a massive process simulation exercise could make it more difficult than expected to achieve the performance advantages of emerging 7nm and 5nm processes.

Nano-electronics research centre imec has worked with Coventor to simulate the process variability of its 7nm BEOL fabrication processes using Coventor’s SEMulator3D virtual fabrication platform. The simulation of a full process window, looking at how multiple parameters of multiple processes interact, would have taken one million wafers to complete using conventional methods.

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Imec, Coventor expand collaboration to optimize 7 nm semiconductor manufacturing processes

• Joint development team leverages SEMulator3D to explore semiconductor process  variation issues at unprecedented levels
• Collaboration team has conducted a massive computer modeling simulation of a million
wafers to explore process variability in 7nm BEOL semiconductor fabrication
• The extending collaboration aims to further advance the availability, yield and cost of
manufacturing processes for the next generation of 7 nm semiconductor products

Leuven, Belgium & Cary, North Carolina, United States – December 7, 2015 – Imec, a
world-leading nanoelectronics research center and Coventor, a leading supplier of semiconductor process development tools, today announced the expansion of a joint development project to explore process variation issues in 7nm semiconductor technology. read more…

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