Coventor recently sponsored an expert panel discussion at IEDM 2017 to discuss how we might advance the semiconductor industry into the next generation of technology. The panel discussed alternative methods to solve fundamental problems of technology scaling, using advances in semiconductor architectures, patterning, metrology, advanced process control, variation reduction, co-optimization and new integration schemes. Our panel included Rick Gottscho, CTO of Lam Research; Mark Dougherty, vice president of advanced module engineering at GlobalFoundries; David Shortt, technical fellow at KLA-Tencor; Gary Zhang, vice president of computational lithography products at ASML; and Shay Wolfling, CTO of Nova Measuring Instruments.
EVENTS & CONFERENCES
- SPIE Advanced Lithography Symposium 2018 – 25 February – 1 March, San Jose, CA
- 2nd Electron Devices Technology and Manufacturing (EDTM) Conference 2018 – March 13-16, 2018, Kobe, Japan
- SEMICON China 2018 – March 14 – 16, 2018, Shanghai, China
- The Smart Systems Integration Conference 2018 – April 11- 12, 2018, Dresden, Germany
TAGS5NM 7 nm ASML BEOL Coventor Directed Self Assembly DSA ETCH EUV GLOBALFOUNDRIES imec INTEL LAM RESEARCH lithography MEMS MEMS+ mems accelerometer mems design MEMS Design Software mems microphone mems simulation MEMS technology Moore's Law multi-patterning Online Articles Press release Process Development Process Integration Process Modeling Process Simulation Process Variability Process variation SADP SAQP Self-Aligned Quadruple Patterning semiconductor process modeling semiconductor process variation SEMulator3D Silicon Designs silicon photonics ST Microelectronics TCAD TSMC virtual fabrication X-Fab