back end of line

Reducing BEOL Parasitic Capacitance using Air Gaps

By: Michael Hargrove, SP&I Engineer

Reducing back-end-of-line (BEOL) interconnect parasitic capacitance remains a focus for advanced technology node development. Porous low-k dielectric materials have been used to achieve reduced capacitance, however, these materials remain fragile and prone to reliability concerns. More recently, air gap has been successfully incorporated into 14nm technology [1], and numerous schemes have been proposed to create the air gap [2-3].  There are many challenges to integrate air gap in BEOL such as process margin for un-landed vias and overall increased process complexity. In this paper, we introduce virtual fabrication (SEMulator3D®) as a means to study air gap process integration optimization and resulting interconnect capacitance reduction. Initial calibration to published air gap data is demonstrated. read more…

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What drives SADP BEOL variability?

By: Michael Hargrove, Semiconductor Process & Integration Engineer

Until EUV lithography becomes a reality, multiple patterning technologies such as triple litho-etch (LELELE), self-aligned double patterning (SADP), and self-aligned quadruple patterning (SAQP) are being used to meet the stringent patterning demands of advanced back-end-of-line (BEOL) technologies.  For the 7nm technology node, patterning requirements include a metal pitch of 40nm or less. This narrow pitch requirement forces the use of spacer based pitch multiplication techniques. Unfortunately, these techniques have high process/lithography variability, which can severely impact RC and overall device performance.

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