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What the Experts Think: Delivering the Next 5 Years of Semiconductor Technology

Coventor recently sponsored an expert panel discussion at IEDM 2017 to discuss how we might advance the semiconductor industry into the next generation of technology.  The panel discussed alternative methods to solve fundamental problems of technology scaling, using advances in semiconductor architectures, patterning, metrology, advanced process control, variation reduction, co-optimization and new integration schemes.  Our panel included Rick Gottscho, CTO of Lam Research; Mark Dougherty, vice president of advanced module engineering at GlobalFoundries; David Shortt, technical fellow at KLA-Tencor; Gary Zhang, vice president of computational lithography products at ASML; and Shay Wolfling, CTO of Nova Measuring Instruments.

The Next 5 Years of Semiconductor Technology

L-R: Ed Sperling (moderator), Shay Wolfling, Rick Gottscho, Mark Dougherty, Gary Zhang, David Shortt

Here are a few expert predictions for the next 5 years of semiconductor technology that came out of the discussion:

FinFETs will get extended to at least to 5nm, and possibly 3nm

Rick Gottscho of Lam Research felt that FinFETs will get extended to at least 5nm, and possibly 3nm.    Shay Wolfing of Nova Measuring Instruments predicted that nanosheet technology could be used after FinFET extensions would not scale further.

EUV will be used at new nodes, followed by High NA Lithography

Gary Zhang of ASML stated that EUV will drive lithography at new nodes, with high-NA as an extension to EUV on the technology roadmap. Gary felt that managing the complexity and the cost of these new lithography techniques will be challenging, but feasible.

Materials and basic structures may diverge by supplier, at 7 nm and beyond

Mark Dougherty of GlobalFoundries noted that suppliers may not align at the end of the day on the same materials and basic structures to scale semiconductor technology. It’s possible that there might be some divergence, such as in back-end-of-line metallurgy.

Metrology can meet future technical challenges, but inspection and measurement costs may rise

Gary Zhang confirmed that 3D measurements below an angstrom are now possible, and that we have metrology solutions available for the near future.   David Shortt of KLA-Tencor asserted that end-to-end cycle time and cost are increasing for inspection and metrology, and that these trends may continue unless technical risk reduction is started early in the development process.

3D NAND technology will continue scaling beyond the existing 48 layer structures

Rick Gottscho stated that he sees a path over the next 10 years to scale 3D NAND manufacturing technology, up to 256 layers.   Rick had some concerns over film stress and challenging etch requirements in meeting this scaling projection.

If you are interested in reading more about this panel, you can find the first part of the panel transcript at Semiconductor Engineering.   Future articles in Semiconductor Engineering will highlight the remainder of the panel discussion, including the expert’s views on the role of advanced process control, variation reduction, co-optimization and new integration schemes in delivering the next 5 years of semiconductor technology.

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Multi-Beam Market Heats Up

se_logoBy Mark Lapedus

The multi-beam e-beam mask writer business is heating up, as Intel and NuFlare have separately entered the emerging market.

In one surprising move, Intel is in the process of acquiring IMS Nanofabrication, a multi-beam e-beam equipment vendor. And separately, e-beam giant NuFlare recently disclosed its new multi-beam mask writer technology.

As a result of the moves, the Intel/IMS duo and NuFlare will now race each other to bring multi-beam mask writers into the market. Still in the R&D stage, these newfangled tools promise to speed up the write times for next-generation photomasks, although there are still challenges to bring this technology into production.

read the full article here

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7nm Lithography Choices

se_logoBy Mark Lapedus

Chipmakers are ramping up their 16nm/14nm logic processes, with 10nm expected to move into early production later this year. Barring a major breakthrough in lithography, chipmakers are using today’s 193nm immersion and multiple patterning for both 16/14nm and 10nm.

Now, chipmakers are focusing on the lithography options for 7nm. For this, they hope to use a combination of two technologies at 7nm—extreme ultraviolet (EUV) lithography, and 193nm immersion with multi-patterning.

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What’s the Next-Gen Litho Tech? Maybe All of Them

semimd_logoBy Jeff Dorsch

The annual SPIE Advanced Lithography symposium in San Jose, Calif., hasn’t offered a clear winner in the next-generation lithography race. It’s becoming clearer, however, that 193i immersion and extreme-ultraviolet lithography will co-exist in the future, while directed self-assembly, nanoimprint lithography, and maybe even electron-beam direct-write technology will fit into the picture, too.

At the same time, plasma deposition and etching processes are assuming a greater interdependence with 193i, especially when it comes to multiple patterning, such as self-aligned double patterning, self-aligned quadruple patterning, and self-aligned octuple patterning (yes, there is such a thing!).

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