By: Mustafa B. Akbulut, Ph.D., Team Lead, Quality Assurance, Semiconductor Solutions
Things were easy for integrators when the pattern they had on the mask ended up being the pattern they wanted on the chip. Multi-patterning schemes such as Self-Aligned Double Patterning (SADP) and Self-Aligned Quadruple Patterning (SAQP) have changed that dramatically. Now, what you have on the mask determines only a part of what you will get at the end. read more…
Tagged BEOL, Coventor, Fin Patterning, multi-patterning, Photolithography, Process Modeling, Process Simulation, Process Variability, SAQP, Self-Aligned Double Patterning, Self-Aligned Quadruple Patterning, Semiconductor Mask, semiconductor process modeling, semiconductor process variation, SEMulator3D, SPIE Advanced Lithography, virtual fabrication
At SPIE Advanced Lithography 2017, Coventor Will Present Results of Studies to Increase Density and Yield of Next-Generation Semiconductor Devices
CARY, NC– February 13, 2017 – Coventor®, Inc., the leading supplier of virtual fabrication solutions for semiconductor devices and micro-electromechanical systems (MEMS), will present findings from its research on advanced semiconductor fabrication processes at SPIE Advanced Lithography 2017. The results of these studies provide insight into techniques for advancing the state-of-the-art in semiconductor technology through use of new and emerging photomask, lithography and process technologies. read more…
Tagged 7 nm, BEOL, Coventor, ETCH, EUV, imec, lithography, multi-patterning, Process Development, Process Modeling, Process Simulation, Process Variability, SAQP, Self-Aligned Quadruple Patterning, semiconductor process modeling, semiconductor process variation, SEMulator3D, virtual fabrication
By: Dalong Zhao – Semiconductor Process & Integration Engineering
Yield and cost have always been critical factors for both manufacturers and designers of semiconductor products. Meeting yield and product cost targets is a continuous challenge, due to new device structures and increasingly complex process innovations introduced to achieve improved product performance at each new technology node. Design for manufacturability (DFM) and design process technology co-optimization (DTCO) are widely used techniques that can ensure the successful delivery of both new processes and products in semiconductor manufacturing. In this article, we will discuss how 3D (3 dimensional) DTCO can be used to improve product yield and accelerate product delivery dates in semiconductor manufacturing. read more…
Tagged Coventor, Design Rule Checks, Design Technology Co-Optimization, DRC, DTCO, hotspot, lithography, multi-patterning, Process Development, Process Modeling, Process Simulation, semiconductor process modeling, semiconductor process variation, SEMulator3D
IMEC Partner Technical Week Review
By: Aurélie Juncker, Semiconductor Process & Integration Engineer
a. Fully aligned Via with Cu recess approach – Gayle Murdoch, b. STT-RAM – Davide Crotti, c. N10 Supernova2 process – Matt Gallagher
In March 2016, Coventor was invited to the biannual Partner Technical Week (PTW) at IMEC in Leuven, Belgium. IMEC, a world-leading research group in nanotechnology, organizes their Partner Technical Week every 6 months to present scientific results to their partners. During this week, a number of specialists from IMEC’s many partner companies also discuss their progress in areas related to IMEC’s research. This event brings together a large number of engineers who are specialists in their domain, and provides an interesting forum to leverage the scientific knowledge gained by IMEC and its partners. read more…
Tagged 7 nm, BEOL, Coventor, DOE, DUV, ETCH, EUV, FEOL, i193, lithography, misalignment, multi-patterning, N7, patterning, virtual fabrication
By Mark Lapedus
Semiconductor Engineering sat down to discuss the foundry business, memory, process technology, lithography and other topics with David Fried, chief technology officer at Coventor, a supplier of predictive modeling tools. What follows are excerpts of that conversation.
SE: Chipmakers are ramping up 16nm/14nm finFETs today, with 10nm and 7nm finFETs just around the corner. What do you see happening at these advanced nodes, particularly at 7nm?
Fried: Most people are predicting evolutionary scaling from 14nm to 10nm to 7nm. It’s doubtful that we will see anything really earth-shattering in these technologies. And so, a lot of the challenges come down to patterning. We are going to see multi-patterning schemes really take hold at more levels. For example, the fins are now based on self-aligned double patterning. People will move into self-aligned quad patterning. The gates are maybe self-aligned double. Now, they will move into self-aligned quad. So, that’s going to be a big expense, because each level is going to have multiple passes and multiple cuts.
read the full article here
Tagged 10NM, 3D NAND, 5NM, ATOMIC-LEVEL VARIABILITY, BEOL, Coventor, DEPOSITION, Directed Self Assembly, DSA, ETCH, EUV, III-V MATERIALS, INTEL, lithography, LOW-K DIELECTRICS, MRAM, multi-patterning, NANOWIRE FETS, RC DELAY, RERAM, SADP, TSMC
By Scotten Jones, SemiWiki
On Tuesday evening December 8th at IEDM, Coventor held a panel discussion entitled the “The Last Half Nanometer”. Coventor is a leading provider of simulation software used to design processes. This is my third year attending the Coventor panel discussion at IEDM and they are always excellent with very strong panels and discussion. The panel was made up of David Fried CTO of Coventor, Alek Chen from ASML, Aaron Theon of IMEC, and Subramanian Iyer from UCLA. Subramanian acted as both a panelist and the moderator.
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Tagged ASML, Coventor, DSA, EUV, imec, Moore's Law, multi-patterning, Process Modeling, Process Variability, semiconductor process modeling, semiconductor process variation