By: Dalong Zhao – Semiconductor Process & Integration Engineering
Yield and cost have always been critical factors for both manufacturers and designers of semiconductor products. Meeting yield and product cost targets is a continuous challenge, due to new device structures and increasingly complex process innovations introduced to achieve improved product performance at each new technology node. Design for manufacturability (DFM) and design process technology co-optimization (DTCO) are widely used techniques that can ensure the successful delivery of both new processes and products in semiconductor manufacturing. In this article, we will discuss how 3D (3 dimensional) DTCO can be used to improve product yield and accelerate product delivery dates in semiconductor manufacturing. read more…
Tagged Coventor, Design Rule Checks, Design Technology Co-Optimization, DRC, DTCO, hotspot, lithography, multi-patterning, Process Development, Process Modeling, Process Simulation, semiconductor process modeling, semiconductor process variation, SEMulator3D
Senior C++ Physics Modeling Engineer – Waltham, MA
Coventor, Inc. is seeking a software engineer with significant C++ experience and familiarity with physical simulation. As a key member of our modeling engine team, you will extend and improve our software, working to implement new physics-based 3D modeling algorithms for semiconductor fabrication processes. You will join a collaborative, highly skilled software development team working on our innovative software tools and solutions for the semiconductor and MEMS manufacturing industries. Our software uses unique, highly efficient numerical modeling and simulation techniques to perform virtual fabrication of state-of-the-art semiconductor and MEMS devices. This is a hands-on software development position, requiring proficiency in C++. Your title, level of responsibility, creative freedom and salary will be commensurate with your education and experience.
- Research, prototype and characterize new modeling algorithms for semiconductor fabrication processes, particularly through perusal of relevant technical literature
- Collaborate to implement new 3D modeling algorithms in our C++ modeling engine
- Extend and maintain our generic, C++ template-based modeling framework
- Optimize modeling algorithms for speed, including profiling and parallel implementation
- Participate in general software engineering tasks, including verification, testing, bug fixing and maintenance of existing code
Required Qualifications (all of the following):
- MS in Engineering, Physics, Computer Science or a related field. PhD degree is a strong plus
- Direct experience in implementation of numerical physics simulation algorithms (PDE solutions through FVM, FEM, FDM, etc.)
- Minimum of 4 years work experience in commercial software development
- Expert level C++ skills, including implementation of template classes
- Strong math skills, including a thorough knowledge of linear algebra and calculus
- Demonstrated ability to design and implement clean, well-organized production code
- Desire to collaborate, contribute to, and learn from a team
Desirable Qualifications (any of the following):
- General knowledge of semiconductor processing technology
- Experience with cross-platform development, on Windows and Linux
- Experience with one or more of: Boost, STL, C++11 or later, Python
This regular, full-time position is located in Waltham, MA. Coventor offers comprehensive benefits and is an EEO/AA Employer. You must be a current legal resident of the U.S. or have a valid U.S. visa to apply for this position. Please e-mail your resume to firstname.lastname@example.org.
Coventor® is the market leader in software solutions for the development of semiconductor process technology, as well as micro-electromechanical systems (MEMS). Coventor serves a worldwide customer base of integrated device manufacturers, memory suppliers, fabless design houses, independent foundries, and R&D organizations. Our SEMulator3D modeling and analysis platform provides fast and accurate ‘virtual fabrication’ of advanced manufacturing processes, allowing engineers to understand manufacturing effects early in the development process and reduce time-consuming and costly silicon learning cycles. Our MEMS design solutions are used to develop MEMS-based products for automotive, aerospace, industrial, defense, and consumer electronics applications, including smart phones, tablets, and gaming systems. Our software and expertise helps customers predict the structures and behavior of their designs before they commit to time-consuming and costly fabrication. The company is headquartered in Cary, NC and has offices in Waltham, MA; Silicon Valley, CA; Tokyo, Japan; Hsinchu, Taiwan; and Paris, France. For more information please visit www.coventor.com.
Coventor’s Virtual Fabrication Platform Addresses Increasingly Complex Semiconductor Process Design Challenges
CARY, NC– June 6, 2016 – Coventor®, Inc., the leading supplier of automated software solutions for semiconductor devices and micro-electromechanical systems (MEMS), today announced the availability of SEMulator3D® 6.0 – the latest version of its semiconductor virtual fabrication platform. This new version further increases the accuracy of the process simulation, geometry and modeling of advanced semiconductor processes with new features, usability enhancements and a new add-on capability for electrical analysis. Along with SEMulator3D 6.0, Coventor is releasing an all-new SEMulator3D Electrical Analysis add-on component that allows seamless resistance and capacitance extraction directly from SEMulator3D process-predictive 3D models. read more…
By: Mattan Kamon, PhD., Distinguished Technologist, R&D, Coventor
But first, more generally, will directed self-assembly (DSA) join Extreme Ultraviolet (EUV) Lithography and next generation multi-patterning techniques to pattern the next memory and logic technologies? Appealing to the wisdom of crowds, the organizers of the 2015 1st International DSA symposium recently surveyed the attendees, and nearly 75% believed DSA would insert into high volume manufacturing within the next 5 years, and nearly 30% predicted insertion within the next 2 years. What is gating insertion? The crowd rated defectivity as the most critical issue facing DSA. This fact adds weight to memory being the first to be patterned with DSA. This is because, as Roel Gronheid from IMEC pointed out last month at the SPIE Advanced Lithography conference , memory chips can tolerate single failing cells through redundancy and so can could tolerate higher defectivity in patterning (roughly 1 defect/cm2 compared to 0.01 defect/cm2 for logic). Defectivity rates for DSA aren’t there yet (according to public information), but are rapidly approaching , . read more…
Tagged 14 nm DRAM process modeling, Directed Self Assembly, DSA, LER, LWR, Process Modeling, Process Simulation, SAQP, Self-Aligned Quadruple Patterning, semiconductor process modeling, Semiconductor Process Simulation, virtual fabrication
By Luke Collins, Tech Design Forum
Directed self assembly (DSA) techniques may offer similar advantages in terms of process variation control as EUV lithography, according to a study carried out using 3D behavioral process modeling techniques.
This could reduce fab cycle times, ease process integration and save costs in advanced semiconductor processes, especially for DRAMs, whose regular structures are well-suited to the use of DSA.
read the full article here
By Scotten Jones, SemiWiki
On Tuesday evening December 8th at IEDM, Coventor held a panel discussion entitled the “The Last Half Nanometer”. Coventor is a leading provider of simulation software used to design processes. This is my third year attending the Coventor panel discussion at IEDM and they are always excellent with very strong panels and discussion. The panel was made up of David Fried CTO of Coventor, Alek Chen from ASML, Aaron Theon of IMEC, and Subramanian Iyer from UCLA. Subramanian acted as both a panelist and the moderator.
read the full article here
Tagged ASML, Coventor, DSA, EUV, imec, Moore's Law, multi-patterning, Process Modeling, Process Variability, semiconductor process modeling, semiconductor process variation
By Luke Collins, Tech Design Forum
New variability issues highlighted by a massive process simulation exercise could make it more difficult than expected to achieve the performance advantages of emerging 7nm and 5nm processes.
Nano-electronics research centre imec has worked with Coventor to simulate the process variability of its 7nm BEOL fabrication processes using Coventor’s SEMulator3D virtual fabrication platform. The simulation of a full process window, looking at how multiple parameters of multiple processes interact, would have taken one million wafers to complete using conventional methods.
read the full article here
• Joint development team leverages SEMulator3D to explore semiconductor process variation issues at unprecedented levels
• Collaboration team has conducted a massive computer modeling simulation of a million
wafers to explore process variability in 7nm BEOL semiconductor fabrication
• The extending collaboration aims to further advance the availability, yield and cost of
manufacturing processes for the next generation of 7 nm semiconductor products
Leuven, Belgium & Cary, North Carolina, United States – December 7, 2015 – Imec, a
world-leading nanoelectronics research center and Coventor, a leading supplier of semiconductor process development tools, today announced the expansion of a joint development project to explore process variation issues in 7nm semiconductor technology. read more…
Tagged 7 nm, 7 nm semiconductor, 7 nm semiconductor manufacturing, 7nm BEOL, Coventor, imec, Process Modeling, semiconductor process, semiconductor process modeling, semiconductor process variation, SEMulator3D