Process Modeling

Coventor Announces SEMulator3D 6.0 and New Electrical Analysis Capabilities

Coventor’s Virtual Fabrication Platform Addresses Increasingly Complex Semiconductor Process Design Challenges

CARY, NC– June 6, 2016 – Coventor®, Inc., the leading supplier of automated software solutions for semiconductor devices and micro-electromechanical systems (MEMS), today announced the availability of SEMulator3D® 6.0 – the latest version of its semiconductor virtual fabrication platform. This new version further increases the accuracy of the process simulation, geometry and modeling of advanced semiconductor processes with new features, usability enhancements and a new add-on capability for electrical analysis. Along with SEMulator3D 6.0, Coventor is releasing an all-new SEMulator3D Electrical Analysis add-on component that allows seamless resistance and capacitance extraction directly from SEMulator3D process-predictive 3D models. read more…

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Will directed self-assembly pattern 14nm DRAM?

By: Mattan Kamon, PhD., Distinguished Technologist, R&D, Coventor

Matt's March 2016 Blog Graphic

But first, more generally, will directed self-assembly (DSA) join Extreme Ultraviolet (EUV) Lithography and next generation multi-patterning techniques to pattern the next memory and logic technologies?  Appealing to the wisdom of crowds, the organizers of the 2015 1st International DSA symposium recently surveyed the attendees, and nearly 75% believed DSA would insert into high volume manufacturing within the next 5 years, and nearly 30% predicted insertion within the next 2 years.   What is gating insertion?  The crowd rated defectivity as the most critical issue facing DSA.  This fact adds weight to memory being the first to be patterned with DSA.  This is because, as Roel Gronheid from IMEC pointed out last month at the SPIE Advanced Lithography conference [1], memory chips can tolerate single failing cells through redundancy and so can could tolerate higher defectivity in patterning (roughly 1 defect/cm2 compared to 0.01 defect/cm2 for logic).  Defectivity rates for DSA aren’t there yet (according to public information), but are rapidly approaching [2], [3]. read more…

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Directed self assembly may offer similar benefits to EUV, process modeling study says

By Luke Collins, Tech Design Forum

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Directed self assembly (DSA) techniques may offer similar advantages in terms of process variation control as EUV lithography, according to a study carried out using 3D behavioral process modeling techniques.

This could reduce fab cycle times, ease process integration and save costs in advanced semiconductor processes, especially for DRAMs, whose regular structures are well-suited to the use of DSA.

read the full article here

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Coventor ASML IMEC: The last half nanometer

By Scotten Jones, SemiWiki
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On Tuesday evening December 8th at IEDM, Coventor held a panel discussion entitled the “The Last Half Nanometer”. Coventor is a leading provider of simulation software used to design processes. This is my third year attending the Coventor panel discussion at IEDM and they are always excellent with very strong panels and discussion. The panel was made up of David Fried CTO of Coventor, Alek Chen from ASML, Aaron Theon of IMEC, and Subramanian Iyer from UCLA. Subramanian acted as both a panelist and the moderator.

read the full article here

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Asymmetric variability issues could impact 7nm processes

By Luke Collins, Tech Design Forum

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New variability issues highlighted by a massive process simulation exercise could make it more difficult than expected to achieve the performance advantages of emerging 7nm and 5nm processes.

Nano-electronics research centre imec has worked with Coventor to simulate the process variability of its 7nm BEOL fabrication processes using Coventor’s SEMulator3D virtual fabrication platform. The simulation of a full process window, looking at how multiple parameters of multiple processes interact, would have taken one million wafers to complete using conventional methods.

read the full article here

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Imec, Coventor expand collaboration to optimize 7 nm semiconductor manufacturing processes

• Joint development team leverages SEMulator3D to explore semiconductor process  variation issues at unprecedented levels
• Collaboration team has conducted a massive computer modeling simulation of a million
wafers to explore process variability in 7nm BEOL semiconductor fabrication
• The extending collaboration aims to further advance the availability, yield and cost of
manufacturing processes for the next generation of 7 nm semiconductor products

Leuven, Belgium & Cary, North Carolina, United States – December 7, 2015 – Imec, a
world-leading nanoelectronics research center and Coventor, a leading supplier of semiconductor process development tools, today announced the expansion of a joint development project to explore process variation issues in 7nm semiconductor technology. read more…

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Intel Announces Production-Ready 22nm 3-D Tri-Gate Transistor

Yesterday Intel announced its readiness for high-volume manufacturing of 3-D tri-gate (FinFET) transistors. Among other benefits, the tri-gate configuration allows Intel to manufacture higher performance fully-depleted devices without resorting to Silicon-On-Insulator (SOI) wafers. The performance gains quoted by Intel over their own 32nm planar transistor technology are impressive, including a 37% speed increase at low voltage , 18% speed increase at high voltage and 50% or greater power reduction at constant performance. All these performance benefits come with only a 2-3% cost increase.
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Process Simulation vs. Process Emulation: is SEMulator3D really TCAD?

I was interested to note that Silvaco has recently listed SEMulator3D as a competitor for their VICTORY Process Cell software on their website. It’s great to be mentioned as a contender in the TCAD process simulation space. But I’d like to take the opportunity to examine the following question – are SEMulator3D and VICTORY Process Cell really direct competitors?

On the surface, both SEMulator3D and VICTORY Process Cell can do some similar things. Both tools are fast, layout driven process modeling engines that are designed to build 3D models of MEMS and semiconductor devices. Both tools can model individual process steps or entire process sequences, and can model a variety of process and device types. And both tools can create meshes suitable for further physics simulation.

read more…

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