Process Simulation

Semiconductor Process and Integration Engineer – South Korea

Semiconductor Process and Integration Engineer – South Korea

We are seeking a BS/MS/PhD-level engineer who has experience and expertise in semiconductor process integration and fabrication. You will work with leading semiconductor companies to implement our virtual fabrication solution for their most advanced development programs, including 10nm CMOS technology and beyond! You will collaborate with the Semiconductor Process & Integration team in the Office of the CTO, along with our highly skilled software development team, to create integration and modeling solutions for industry-critical manufacturing challenges. Our tight-knit team of creative engineers is critical in leading customers into the methodology of virtual fabrication.

This is a hands-on engineering position, requiring proficiency in full flow semiconductor process integration, as well as strong communication and presentation skills. Your title, level of responsibility, creative freedom and salary will be commensurate with your education and experience.

Location: South Korea. This position requires residency in South Korea with a substantial amount of time at customer sites in South Korea. Work is expected to be partly based at customer/partner sites. Travel is expected.

Required Qualifications:

Education: Bachelor’s degree required, Master’s degree preferred, in related fields of Electrical Engineering, Chemical Engineering, Materials Science or Applied Physics.

Experience: Semiconductor Technology and Processing education and experience is required. Relevant employment experience in the semiconductor industry is required.

Skills: Semiconductor Processing and Integration, Semiconductor Device Physics (preferred), Computer-Aided Design (CAD) and Modeling, Python scripting language, Technical Writing , Communication and Presentation.

If you are interested in this opportunity and you are authorized to work in South Korea, e-mail your cover letter and CV in English to job1826@coventor.com.

About Coventor:

Coventor, Inc. (www.coventor.com) is the global market leader in virtual fabrication solutions for semiconductor technologies and design automation solutions for microelectromechanical systems (MEMS). Coventor serves a worldwide customer base of integrated device manufacturers, independent foundries, equipment makers, and R&D organizations that develop semiconductor and MEMS technologies for consumer, automotive, aerospace, industrial, and defense uses. Coventor’s predictive modeling tools and expertise enable its customers to dramatically reduce silicon learning cycles, giving them a time-to-market advantage and reducing technology development costs. The company is headquartered in Cary, NC and has offices in Waltham, MA; Silicon Valley, CA; Tokyo, Japan; Hsinchu, Taiwan; and Paris, France.

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Semiconductor Process and Integration Engineer – Taiwan

Semiconductor Process and Integration Engineer – Taiwan

We are seeking a BS/MS/PhD-level engineer who has experience and expertise in semiconductor process integration and fabrication. You will work with leading semiconductor companies to implement our virtual fabrication solution for their most advanced development programs, including 10nm CMOS technology and beyond! You will collaborate with the Semiconductor Process & Integration team in the Office of the CTO, along with our highly skilled software development team, to create integration and modeling solutions for industry-critical manufacturing challenges. Our tight-knit team of creative engineers is critical in leading customers into the methodology of virtual fabrication.

This is a hands-on engineering position, requiring proficiency in full flow semiconductor process integration, as well as strong communication and presentation skills. Your title, level of responsibility, creative freedom and salary will be commensurate with your education and experience.

Location: Taiwan. This position requires residency in Taiwan with a substantial amount of time at customer sites in Taiwan. Work is expected to be partly based at customer/partner sites. Travel is expected.

Required Qualifications:

Education: Bachelor’s degree required, Master’s degree preferred, in related fields of Electrical Engineering, Chemical Engineering, Materials Science or Applied Physics.

Experience: Semiconductor Technology and Processing education and experience is required. Relevant employment experience in the semiconductor industry is required.

Skills: Semiconductor Processing and Integration, Semiconductor Device Physics (preferred), Computer-Aided Design (CAD) and Modeling, Python scripting language, Technical Writing , Communication and Presentation.

If you are interested in this opportunity and you are authorized to work in Taiwan, e-mail your cover letter and CV in English to job1825@coventor.com.

About Coventor:

Coventor, Inc. (www.coventor.com) is the global market leader in virtual fabrication solutions for semiconductor technologies and design automation solutions for microelectromechanical systems (MEMS). Coventor serves a worldwide customer base of integrated device manufacturers, independent foundries, equipment makers, and R&D organizations that develop semiconductor and MEMS technologies for consumer, automotive, aerospace, industrial, and defense uses. Coventor’s predictive modeling tools and expertise enable its customers to dramatically reduce silicon learning cycles, giving them a time-to-market advantage and reducing technology development costs. The company is headquartered in Cary, NC and has offices in Waltham, MA; Silicon Valley, CA; Tokyo, Japan; Hsinchu, Taiwan; and Paris, France.

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What drives SADP BEOL variability?

By: Michael Hargrove, Semiconductor Process & Integration Engineer

Until EUV lithography becomes a reality, multiple patterning technologies such as triple litho-etch (LELELE), self-aligned double patterning (SADP), and self-aligned quadruple patterning (SAQP) are being used to meet the stringent patterning demands of advanced back-end-of-line (BEOL) technologies.  For the 7nm technology node, patterning requirements include a metal pitch of 40nm or less. This narrow pitch requirement forces the use of spacer based pitch multiplication techniques. Unfortunately, these techniques have high process/lithography variability, which can severely impact RC and overall device performance.

read more…

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Photoresist shape in 3D: Understanding how small variations in photoresist shape significantly impact multi-patterning yield

By: Mustafa B. Akbulut, Ph.D., Team Lead, Quality Assurance, Semiconductor Solutions

Things were easy for integrators when the pattern they had on the mask ended up being the pattern they wanted on the chip. Multi-patterning schemes such as Self-Aligned Double Patterning (SADP) and Self-Aligned Quadruple Patterning (SAQP) have changed that dramatically. Now, what you have on the mask determines only a part of what you will get at the end. read more…

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AIM Photonics Welcomes Coventor as Newest Member

 

 

 

 

For Immediate Release: March 16, 2017

Contact:
Laura Magee (ESD) | laura.magee@esd.ny.gov | (716) 846-8239 | (800) 260-7313
ESD Press Office | PressOffice@esd.ny.gov | (800) 260-7313
Steve Ference (AIM) | sference@sunypoly.edu | 518-956-7319

CUS-Backed Initiative Taps Process Modeling Specialist to Enable Manufacturing of High-Yield, High-Performance Integrated Photonic Designs

Today’s Announcement Builds On Progress Of Finger Lakes Forward, The Region’s Award-Winning Strategic Plan To Generate Robust Economic Growth And Community Development

ROCHESTER, NY and CARY, NCThe American Institute for Manufacturing Integrated Photonics (AIM Photonics), a public-private partnership advancing the nation’s photonics manufacturing capabilities, and Coventor®, Inc., a semiconductor process modeling software company, today announced Coventor as the newest member of AIM Photonics. Coventor will provide access to its unique, physics-driven 3D modeling technology to improve the performance and manufacturability of complex, integrated photonic designs. read more…

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Semiconductor Process Development: Finding a Faster Way to Profitability

By: Katherine Gambino, Strategic Accounts Manager

Intel Fab

Building a chip fabrication facility requires billions of dollars in investment for land, buildings, processing equipment, chemical and hazardous material safety, not to mention the deployment of hundreds of highly experienced process engineering and manufacturing personnel. Bringing up an advanced semiconductor process in any fab, new or established, is a several-hundred-million dollar effort, typically requiring two or more years of experimentation with process equipment and process recipes, led by engineers with years of process integration and chip manufacturing expertise.

read more…

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Coventor Unveils New Scientific Findings on Lithography Processing For Improved Semiconductor Scalability and Performance

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At SPIE Advanced Lithography 2017, Coventor Will Present Results of Studies to Increase Density and Yield of Next-Generation Semiconductor Devices

CARY, NC– February 13, 2017 – Coventor®, Inc., the leading supplier of virtual fabrication solutions for semiconductor devices and micro-electromechanical systems (MEMS), will present findings from its research on advanced semiconductor fabrication processes at SPIE Advanced Lithography 2017. The results of these studies provide insight into techniques for advancing the state-of-the-art in semiconductor technology through use of new and emerging photomask, lithography and process technologies. read more…

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The Value of Integrating Process Models with TCAD Simulation (and some tips on how to do it)

By: Shi Hao (Jacky) Huang, PhD, Semiconductor Process & Integration Engineer

Coventor January 2017 Blog Graphic

Coventor January 2017 Blog Graphic 2

 

 

 

 

Nowadays, novel semiconductor technologies have brought complex process flows to the fab.   These process flows are needed to support the manufacturing of advanced 3D semiconductor structures. It can be helpful to model process flows, and their effect on a novel device, prior to physical fabrication.

read more…

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