SAQP

What drives SADP BEOL variability?

By: Michael Hargrove, Semiconductor Process & Integration Engineer

Until EUV lithography becomes a reality, multiple patterning technologies such as triple litho-etch (LELELE), self-aligned double patterning (SADP), and self-aligned quadruple patterning (SAQP) are being used to meet the stringent patterning demands of advanced back-end-of-line (BEOL) technologies.  For the 7nm technology node, patterning requirements include a metal pitch of 40nm or less. This narrow pitch requirement forces the use of spacer based pitch multiplication techniques. Unfortunately, these techniques have high process/lithography variability, which can severely impact RC and overall device performance.

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Photoresist shape in 3D: Understanding how small variations in photoresist shape significantly impact multi-patterning yield

By: Mustafa B. Akbulut, Ph.D., Team Lead, Quality Assurance, Semiconductor Solutions

Things were easy for integrators when the pattern they had on the mask ended up being the pattern they wanted on the chip. Multi-patterning schemes such as Self-Aligned Double Patterning (SADP) and Self-Aligned Quadruple Patterning (SAQP) have changed that dramatically. Now, what you have on the mask determines only a part of what you will get at the end. read more…

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Coventor Unveils New Scientific Findings on Lithography Processing For Improved Semiconductor Scalability and Performance

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At SPIE Advanced Lithography 2017, Coventor Will Present Results of Studies to Increase Density and Yield of Next-Generation Semiconductor Devices

CARY, NC– February 13, 2017 – Coventor®, Inc., the leading supplier of virtual fabrication solutions for semiconductor devices and micro-electromechanical systems (MEMS), will present findings from its research on advanced semiconductor fabrication processes at SPIE Advanced Lithography 2017. The results of these studies provide insight into techniques for advancing the state-of-the-art in semiconductor technology through use of new and emerging photomask, lithography and process technologies. read more…

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BEOL Barricades: Navigating Future Yield, Reliability and Cost Challenges

By: David Fried, Ph.D., Chief Technology Officer, Semiconductor

Figure 1. M2-V1 process flow after (a) M2-L1 lithography, (b) M2-L2 litho, (c) V1 partial etch, (d) BLok open and (e) CuBS.

Coventor recently assembled an expert panel at IEDM 2016, to discuss changes to BEOL process technology that would be needed to continue dimensional scaling to 7 nm and lower. We asked our panelists questions such as: read more…

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Will directed self-assembly pattern 14nm DRAM?

By: Mattan Kamon, PhD., Distinguished Technologist, R&D, Coventor

Matt's March 2016 Blog Graphic

But first, more generally, will directed self-assembly (DSA) join Extreme Ultraviolet (EUV) Lithography and next generation multi-patterning techniques to pattern the next memory and logic technologies?  Appealing to the wisdom of crowds, the organizers of the 2015 1st International DSA symposium recently surveyed the attendees, and nearly 75% believed DSA would insert into high volume manufacturing within the next 5 years, and nearly 30% predicted insertion within the next 2 years.   What is gating insertion?  The crowd rated defectivity as the most critical issue facing DSA.  This fact adds weight to memory being the first to be patterned with DSA.  This is because, as Roel Gronheid from IMEC pointed out last month at the SPIE Advanced Lithography conference [1], memory chips can tolerate single failing cells through redundancy and so can could tolerate higher defectivity in patterning (roughly 1 defect/cm2 compared to 0.01 defect/cm2 for logic).  Defectivity rates for DSA aren’t there yet (according to public information), but are rapidly approaching [2], [3]. read more…

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7nm Lithography Choices

se_logoBy Mark Lapedus

Chipmakers are ramping up their 16nm/14nm logic processes, with 10nm expected to move into early production later this year. Barring a major breakthrough in lithography, chipmakers are using today’s 193nm immersion and multiple patterning for both 16/14nm and 10nm.

Now, chipmakers are focusing on the lithography options for 7nm. For this, they hope to use a combination of two technologies at 7nm—extreme ultraviolet (EUV) lithography, and 193nm immersion with multi-patterning.

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Directed self assembly may offer similar benefits to EUV, process modeling study says

By Luke Collins, Tech Design Forum

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Directed self assembly (DSA) techniques may offer similar advantages in terms of process variation control as EUV lithography, according to a study carried out using 3D behavioral process modeling techniques.

This could reduce fab cycle times, ease process integration and save costs in advanced semiconductor processes, especially for DRAMs, whose regular structures are well-suited to the use of DSA.

read the full article here

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