semiconductor process modeling

Coventor Unveils New Scientific Findings on Lithography Processing For Improved Semiconductor Scalability and Performance

Posted in: Press Releases by Marketing | Comments Off on Coventor Unveils New Scientific Findings on Lithography Processing For Improved Semiconductor Scalability and Performance Monday, February 13, 2017

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At SPIE Advanced Lithography 2017, Coventor Will Present Results of Studies to Increase Density and Yield of Next-Generation Semiconductor Devices

CARY, NC– February 13, 2017 – Coventor®, Inc., the leading supplier of virtual fabrication solutions for semiconductor devices and micro-electromechanical systems (MEMS), will present findings from its research on advanced semiconductor fabrication processes at SPIE Advanced Lithography 2017. The results of these studies provide insight into techniques for advancing the state-of-the-art in semiconductor technology through use of new and emerging photomask, lithography and process technologies. read more…

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The Value of Integrating Process Models with TCAD Simulation (and some tips on how to do it)

Posted in: Coventor Blog by Marketing | Comments Off on The Value of Integrating Process Models with TCAD Simulation (and some tips on how to do it) Friday, January 20, 2017

By: Shi Hao (Jacky) Huang, PhD, Semiconductor Process & Integration Engineer

Coventor January 2017 Blog Graphic

Coventor January 2017 Blog Graphic 2

 

 

 

 

Nowadays, novel semiconductor technologies have brought complex process flows to the fab.   These process flows are needed to support the manufacturing of advanced 3D semiconductor structures. It can be helpful to model process flows, and their effect on a novel device, prior to physical fabrication.

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Coventor in the News – Silicon Photonics

Posted in: Press Releases by Marketing | Comments Off on Coventor in the News – Silicon Photonics Tuesday, January 3, 2017

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Coventor in the News

Photonics in Silicon R&D Toward Tb/s

By Ed Korczynski, Sr. Technical Editor, Semiconductor Manufacturing & Design

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The client:server computing paradigm colloquially referred to as the “Cloud” results in a need for extremely efficient Cloud server hardware, and from first principles the world can save a lot of energy resources if servers run on photonics instead of electronics. Though the potential for cost-savings is well known, the challenge of developing cost-effective integrated photonics solutions remains. Today, discrete compound-semiconductor chips function as transmitters, multiplexers (MUX), and receivers of photons, while many global organizations pursue the vision of lower-cost integrated silicon (Si) photonics circuits. read more…

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Bringing Advanced Semiconductor Manufacturing Technologies to Higher Education

Posted in: Coventor Blog by Marketing | Comments Off on Bringing Advanced Semiconductor Manufacturing Technologies to Higher Education Wednesday, November 16, 2016

By: Jimmy Gu, Ph.D., Semiconductor Process & Integration Engineer, Coventor

Campus image for November 2016 blog

Universities and other institutions of higher learning play a key role in developing our next generation of semiconductor technologies. Along with the theory of semiconductor technology, our next generation of scientists and engineers must learn about the practical methods used to design and manufacture the latest generation of semiconductor products. read more…

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Achieving the Vision of Silicon Photonics Processing

Posted in: Coventor Blog by Marketing | Comments Off on Achieving the Vision of Silicon Photonics Processing Tuesday, October 18, 2016

By: Sandy Wen, MSEE, Semiconductor Process and Integration Engineer, Coventor

Silicon Photonics Test Die

Silicon Photonics Test Die

With the increasing need for faster data transfer rates, the transition from electrical to optical signaling in data processing is inevitable.   Copper cabling cannot keep up with the upcoming data center bandwidth requirements, for applications such as multimedia streaming and high performance computing.  One technology that could enable true optical communication is silicon photonics. read more…

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Design Process Technology Co-Optimization for Manufacturability

Posted in: Coventor Blog by Marketing | Comments Off on Design Process Technology Co-Optimization for Manufacturability Wednesday, September 21, 2016

By:   Dalong Zhao – Semiconductor Process & Integration Engineering

Yield and cost have always been critical factors for both manufacturers and designers of semiconductor products.   Meeting yield and product cost targets is a continuous challenge, due to new device structures and increasingly complex process innovations introduced to achieve improved product performance at each new technology node.  Design for manufacturability (DFM) and design process technology co-optimization (DTCO) are widely used techniques that can ensure the successful delivery of both new processes and products in semiconductor manufacturing.   In this article, we will discuss how 3D (3 dimensional) DTCO can be used to improve product yield and accelerate product delivery dates in semiconductor manufacturing. read more…

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Coventor Announces SEMulator3D 6.0 and New Electrical Analysis Capabilities

Posted in: Press Releases by Marketing | Comments Off on Coventor Announces SEMulator3D 6.0 and New Electrical Analysis Capabilities Tuesday, June 7, 2016

Coventor’s Virtual Fabrication Platform Addresses Increasingly Complex Semiconductor Process Design Challenges

CARY, NC– June 6, 2016 – Coventor®, Inc., the leading supplier of automated software solutions for semiconductor devices and micro-electromechanical systems (MEMS), today announced the availability of SEMulator3D® 6.0 – the latest version of its semiconductor virtual fabrication platform. This new version further increases the accuracy of the process simulation, geometry and modeling of advanced semiconductor processes with new features, usability enhancements and a new add-on capability for electrical analysis. Along with SEMulator3D 6.0, Coventor is releasing an all-new SEMulator3D Electrical Analysis add-on component that allows seamless resistance and capacitance extraction directly from SEMulator3D process-predictive 3D models. read more…

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Will directed self-assembly pattern 14nm DRAM?

Posted in: Coventor Blog by Marketing | Comments Off on Will directed self-assembly pattern 14nm DRAM? Thursday, March 17, 2016

By: Mattan Kamon, PhD., Distinguished Technologist, R&D, Coventor

Matt's March 2016 Blog Graphic

But first, more generally, will directed self-assembly (DSA) join Extreme Ultraviolet (EUV) Lithography and next generation multi-patterning techniques to pattern the next memory and logic technologies?  Appealing to the wisdom of crowds, the organizers of the 2015 1st International DSA symposium recently surveyed the attendees, and nearly 75% believed DSA would insert into high volume manufacturing within the next 5 years, and nearly 30% predicted insertion within the next 2 years.   What is gating insertion?  The crowd rated defectivity as the most critical issue facing DSA.  This fact adds weight to memory being the first to be patterned with DSA.  This is because, as Roel Gronheid from IMEC pointed out last month at the SPIE Advanced Lithography conference [1], memory chips can tolerate single failing cells through redundancy and so can could tolerate higher defectivity in patterning (roughly 1 defect/cm2 compared to 0.01 defect/cm2 for logic).  Defectivity rates for DSA aren’t there yet (according to public information), but are rapidly approaching [2], [3]. read more…

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