SEMulator3D

SEMulator3D Honored as UBM ACE Award Finalist

For Immediate Release
For more information, contact:
Toni Sottak
(408) 876-4418
toni@wiredislandpr.com

SEMulator3D Honored as UBM ACE Award Finalist

Coventor’s Virtual Fabrication Platform Recognized for Significantly Improving Electronics Manufacturing

CARY, NC– November 17, 2017 – Coventor®, Inc. a Lam Research Company and leading supplier of virtual fabrication solutions for semiconductor and micro-electromechanical systems (MEMS) devices, today announced its 3D virtual fabrication platform, SEMulator3D®, has been named a finalist in UBM’s annual ACE Awards competition.

The ACE (Annual Creativity in Electronics) Awards, in partnership with EE Times and EDN, showcase the best of the best in today’s electronics industry, including the hottest new products, start-up companies, design teams, executives, and more. ACE finalists and winners are hand selected by a panel of EE Times and EDN editors as well as independent judges from the across the industry. read more…

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Reducing BEOL Parasitic Capacitance using Air Gaps

By: Michael Hargrove, SP&I Engineer

Reducing back-end-of-line (BEOL) interconnect parasitic capacitance remains a focus for advanced technology node development. Porous low-k dielectric materials have been used to achieve reduced capacitance, however, these materials remain fragile and prone to reliability concerns. More recently, air gap has been successfully incorporated into 14nm technology [1], and numerous schemes have been proposed to create the air gap [2-3].  There are many challenges to integrate air gap in BEOL such as process margin for un-landed vias and overall increased process complexity. In this paper, we introduce virtual fabrication (SEMulator3D®) as a means to study air gap process integration optimization and resulting interconnect capacitance reduction. Initial calibration to published air gap data is demonstrated. read more…

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Using Advanced Statistical Analysis to improve FinFET transistor performance

By: Jimmy Gu, SP&I Staff Engineer

Trial and error wafer fabrication is commonly used to study the effect of process changes in the development of FinFET and other advanced semiconductor technologies.  Due to the interaction of upstream unit process parameters (such as deposition conformality, etch anisotropy, selectivity) during actual fabrication, variations based upon process changes can be highly complex. Process simulators that mimic fab unit processes can now be used to model these complex interactions.  They can also help process engineers identify important process and/or design parameters that drive certain critical targets such as CDs, yield limiting spacing, 3D design rule violations, resistance/capacitance, and other process and design issues.   The number of possible parameters that affect device performance and yield can be quite large, so statistical analysis can provide useful insight and help identify critical performance parameters.  Coventor’s SEMulator3D virtual fabrication (or process simulation) platform contains an analytics module for conducting virtual design-of-experiments and statistical analysis. I would like to use an example of a 14nm FinFET process flow in SEMulator3D to identify important process parameters that drive fin top CD, which is a key metric for transistor performance.

read more…

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Semiconductor Process and Integration Engineer – South Korea

Semiconductor Process and Integration Engineer – South Korea

We are seeking a BS/MS/PhD-level engineer who has experience and expertise in semiconductor process integration and fabrication. You will work with leading semiconductor companies to implement our virtual fabrication solution for their most advanced development programs, including 10nm CMOS technology and beyond! You will collaborate with the Semiconductor Process & Integration team in the Office of the CTO, along with our highly skilled software development team, to create integration and modeling solutions for industry-critical manufacturing challenges. Our tight-knit team of creative engineers is critical in leading customers into the methodology of virtual fabrication.

This is a hands-on engineering position, requiring proficiency in full flow semiconductor process integration, as well as strong communication and presentation skills. Your title, level of responsibility, creative freedom and salary will be commensurate with your education and experience.

Location: South Korea. This position requires residency in South Korea with a substantial amount of time at customer sites in South Korea. Work is expected to be partly based at customer/partner sites. Travel is expected.

Required Qualifications:

Education: Bachelor’s degree required, Master’s degree preferred, in related fields of Electrical Engineering, Chemical Engineering, Materials Science or Applied Physics.

Experience: Semiconductor Technology and Processing education and experience is required. Relevant employment experience in the semiconductor industry is required.

Skills: Semiconductor Processing and Integration, Semiconductor Device Physics (preferred), Computer-Aided Design (CAD) and Modeling, Python scripting language, Technical Writing , Communication and Presentation.

If you are interested in this opportunity and you are authorized to work in South Korea, e-mail your cover letter and CV in English to job1826@coventor.com.

About Coventor:

Coventor, Inc. (www.coventor.com) is the global market leader in virtual fabrication solutions for semiconductor technologies and design automation solutions for microelectromechanical systems (MEMS). Coventor serves a worldwide customer base of integrated device manufacturers, independent foundries, equipment makers, and R&D organizations that develop semiconductor and MEMS technologies for consumer, automotive, aerospace, industrial, and defense uses. Coventor’s predictive modeling tools and expertise enable its customers to dramatically reduce silicon learning cycles, giving them a time-to-market advantage and reducing technology development costs. The company is headquartered in Cary, NC and has offices in Waltham, MA; Silicon Valley, CA; Tokyo, Japan; Hsinchu, Taiwan; and Paris, France.

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What drives SADP BEOL variability?

By: Michael Hargrove, Semiconductor Process & Integration Engineer

Until EUV lithography becomes a reality, multiple patterning technologies such as triple litho-etch (LELELE), self-aligned double patterning (SADP), and self-aligned quadruple patterning (SAQP) are being used to meet the stringent patterning demands of advanced back-end-of-line (BEOL) technologies.  For the 7nm technology node, patterning requirements include a metal pitch of 40nm or less. This narrow pitch requirement forces the use of spacer based pitch multiplication techniques. Unfortunately, these techniques have high process/lithography variability, which can severely impact RC and overall device performance.

read more…

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Photoresist shape in 3D: Understanding how small variations in photoresist shape significantly impact multi-patterning yield

By: Mustafa B. Akbulut, Ph.D., Team Lead, Quality Assurance, Semiconductor Solutions

Things were easy for integrators when the pattern they had on the mask ended up being the pattern they wanted on the chip. Multi-patterning schemes such as Self-Aligned Double Patterning (SADP) and Self-Aligned Quadruple Patterning (SAQP) have changed that dramatically. Now, what you have on the mask determines only a part of what you will get at the end. read more…

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AIM Photonics Welcomes Coventor as Newest Member

 

 

 

 

For Immediate Release: March 16, 2017

Contact:
Laura Magee (ESD) | laura.magee@esd.ny.gov | (716) 846-8239 | (800) 260-7313
ESD Press Office | PressOffice@esd.ny.gov | (800) 260-7313
Steve Ference (AIM) | sference@sunypoly.edu | 518-956-7319

CUS-Backed Initiative Taps Process Modeling Specialist to Enable Manufacturing of High-Yield, High-Performance Integrated Photonic Designs

Today’s Announcement Builds On Progress Of Finger Lakes Forward, The Region’s Award-Winning Strategic Plan To Generate Robust Economic Growth And Community Development

ROCHESTER, NY and CARY, NCThe American Institute for Manufacturing Integrated Photonics (AIM Photonics), a public-private partnership advancing the nation’s photonics manufacturing capabilities, and Coventor®, Inc., a semiconductor process modeling software company, today announced Coventor as the newest member of AIM Photonics. Coventor will provide access to its unique, physics-driven 3D modeling technology to improve the performance and manufacturability of complex, integrated photonic designs. read more…

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Coventor Unveils New Scientific Findings on Lithography Processing For Improved Semiconductor Scalability and Performance

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At SPIE Advanced Lithography 2017, Coventor Will Present Results of Studies to Increase Density and Yield of Next-Generation Semiconductor Devices

CARY, NC– February 13, 2017 – Coventor®, Inc., the leading supplier of virtual fabrication solutions for semiconductor devices and micro-electromechanical systems (MEMS), will present findings from its research on advanced semiconductor fabrication processes at SPIE Advanced Lithography 2017. The results of these studies provide insight into techniques for advancing the state-of-the-art in semiconductor technology through use of new and emerging photomask, lithography and process technologies. read more…

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