May 17, 2022

Quantum Computers and CMOS Semiconductors: A Review and Future Predictions

With the advent of quantum computing, the need for peripheral fault-tolerant logic control circuitry has reached new heights. In classical computation, the unit of information is a “1” or “0”. […]
July 20, 2021

Advancing to the 3nm Node and Beyond: Technology, Challenges and Solutions

It seems like yesterday that FinFETs were the answer to device scaling limitations imposed by shrinking gate lengths and required electrostatics. The introduction of FinFETs began at the 22 nm […]
June 29, 2020

Semiconductor Memory Evolution and Current Challenges

The very first all-electronic memory was the Williams-Kilburn tube, developed in 1947 at Manchester University. It used a cathode ray tube to store bits as dots on the screen’s surface. […]
April 18, 2019

Connecting Wafer Level Parasitic Extraction and Netlisting

The semiconductor technology simulation world is typically divided into device-level TCAD (technology CAD) and circuit-level compact modeling. Larger EDA companies provide high-level design simulation tools that perform LVS (layout vs. […]
August 16, 2018

A Review of Silicon Photonics: Using Process Simulation to Design Silicon Photonics Devices

With the end of Moore’s Law rapidly approaching, or as some folks say – “already here”, new applications of older technologies are gaining attention. One specific area of interest is […]
April 17, 2018

Transistor-Level Performance Evaluation Based on Wafer-Level Process Modeling

Three years ago, I wrote a blog entitled “Linking Virtual Wafer Fabrication Modeling with Device-level TCAD Simulation” in which I described the seamless connection between the SEMulator3D® virtual wafer fabrication […]
January 17, 2018

Future Outlook: The Advantages of Fully Depleted Silicon on Insulator (FD-SOI) Technology

If my memory serves me well, it was at the 1989 Device Research Conference where the potential merits of SOI (Silicon on Insulator) technology were discussed in a heated evening […]
October 18, 2017

Reducing BEOL Parasitic Capacitance using Air Gaps

Reducing back-end-of-line (BEOL) interconnect parasitic capacitance remains a focus for advanced technology node development. Porous low-k dielectric materials have been used to achieve reduced capacitance, however, these materials remain fragile […]
May 17, 2017

What drives SADP BEOL variability?

Until EUV lithography becomes a reality, multiple patterning technologies such as triple litho-etch (LELELE), self-aligned double patterning (SADP), and self-aligned quadruple patterning (SAQP) are being used to meet the stringent […]
July 3, 2014

Linking Virtual Wafer Fabrication Modeling with Device-level TCAD Simulation

Most process/device simulation tools are TCAD-based. By this, I mean they share a common platform which connects the process simulator to the device simulator, usually using the same mesh structure. […]