David Fried, vice president of computational products at Lam Research, examines increasing process variation and interactions between various types of variation, why different approaches are necessary to improve yield and continue scaling.
How to deal with variation, and interactions between various types of variation.
Posted in: Coventor Blog by Sandra Liu | Comments Off on Advanced Patterning Techniques for 3D NAND DevicesThursday, August 1, 2019
By: Yu De Chen, Jacky Huang
Driven by Moore’s law, memory and logic semiconductor manufacturers pursue higher transistor density to improve product cost and performance . In NAND Flash technologies, this has led to the market dominance of 3D structures instead of 2D planar devices. Device density can be linearly increased by increasing stack layer counts in a 3D NAND device . At the same time, patterning scheme optimization can also enhance 3D NAND effective device density. In this discussion, we will analyze various patterning schemes for staircase and slit structures at different TCAT (Terabit Cell Array Transistor) 3D NAND nodes. We will compare these schemes to understand their impact on effective transistor density. The schemes and data used in this study are based upon (or inferred from) tear down reports published by TechInsights®. Variations in patterning schemes, and the resulting virtual structures, were modeled using the SEMulator3D® semiconductor platform. read more…
Posted in: Press Coverage by Sandra Liu | Comments Off on Video: “Scaling technology nodes without moving to new transistor architectures”Monday, June 24, 2019
David Fried, vice president of computational products at Lam Research, looks at shrinking tolerances at advanced processes, how that affects variation in semiconductor manufacturing, and what can be done to achieve the benefits of scaling without moving to new transistor architectures.