Author Archives: Sandra Liu

Connecting Wafer Level Parasitic Extraction and Netlisting

By: Michael Hargrove, SP&I Engineer

The semiconductor technology simulation world is typically divided into device-level TCAD (technology CAD) and circuit-level compact modeling. Larger EDA companies provide high-level design simulation tools that perform LVS (layout vs. schematic), DRC (design rule checking), and many other software solutions that facilitate the entire design process at the most advanced technology nodes. In this blog, I’d like to focus on the design of silicon-level connections between devices and wires in the backend-of-line (BEOL). These connections run across chips and connect various nodes to each other, and ultimately form circuits on the device. read more…

EDA and Foundry Collaboration Speeds MEMS Sensor Design

By Christine Dufour (Coventor) and Viraja and Sharma (X-FAB)

Pressure Sensor (Courtesy X-FAB)

Pressure Sensor (Courtesy: X-FAB)

New MEMS-based products are constantly emerging, fueled by the Internet of Things (IoT), autonomous driving, smart manufacturing and healthcare applications. The MEMS pressure sensor market is no exception to this trend1. Its growth has been driven mainly by automotive applications such as tire pressure management system (TPMS) regulations in China, fuel and ignition systems, thermal systems, oil-pressure monitoring, and indoor and outdoor navigation systems. Easy to customize and integrate, miniature, sensitive, accurate and low-power MEMS devices are especially well-suited to the accuracy, power consumption, sensitivity and miniaturization that pressure sensors require. read more…

Transducers 2019 – Berlin, Germany – June 23-27, 2019

Coventor is exhibiting!

IITC/ MAM – Brussels, Belgium – June 3-6, 2019

Coventor / Lam is participating!

DAC 2019 – Las Vegas, NV – June 2-6, 2019

Coventor is exhibiting! See us at booth #835.

Improving SAQP Patterning Yield using Virtual Fabrication and Advanced Process Control

By:  Benjamin Vincent, Ph.D., Staff Engineer, Semiconductor Process & Integration

Advanced logic scaling has created some difficult technical challenges,  including a requirement for highly dense patterning. Imec recently confronted this challenge, by working toward the use of Metal 2 (M2) line patterning with a 16 nm half-pitch for their 7nm node (equivalent to a 5nm foundry node). Self-Aligned Quadruple Patterning (SAQP) was investigated as an alternative path to Extreme Ultra-Violet (EUV) lithography for this line patterning application.  At the 2019 SPIE Advanced Lithography conference, Coventor personnel demonstrated how virtual process modeling (combined with advanced process control) could provide enhanced patterning yield and enable SAQP patterning at this tight pitch (See Complete White Paper). A summary of the team’s methodology and results are included below. read more…

MEF 2019 – Tokyo, Japan – April 24-25, 2019

Coventor is exhibiting!    

Using Sensor Data To Improve Yield And Uptime

By ED SPERLING

Semiconductor equipment vendors are starting to add more sensors into their tools in an effort to improve fab uptime and wafer yield, and to reduce cost of ownership and chip failures.

Massive amounts of data gleaned from those tools is expected to provide far more detail than in the past about multiple types and sources of variation, including when and where that variation occurred and how, when and why equipment failures occur. Combined with data about device failures in the field, along with such things as design layout and verification, it’s becoming possible to create a detailed timeline of how chips were designed, manufactured and what goes wrong along the way. That, in turn, can be used to improve quality, identify potential sources of defects, and add increased efficiency into processes.

read the full article here