Author Archives: Sandra Liu

Video: “Process Window Optimization”

David Fried, vice president of computational products at Lam Research, examines increasing process variation and interactions between various types of variation, why different approaches are necessary to improve yield and continue scaling.

How to deal with variation, and interactions between various types of variation.

[Video Attribution: Semiconductor Engineering]

Advanced Patterning Techniques for 3D NAND Devices

By: Yu De Chen, Jacky Huang

Introduction

Driven by Moore’s law, memory and logic semiconductor manufacturers pursue higher transistor density to improve product cost and performance [1]. In NAND Flash technologies, this has led to the market dominance of 3D structures instead of 2D planar devices. Device density can be linearly increased by increasing stack layer counts in a 3D NAND device [2]. At the same time, patterning scheme optimization can also enhance 3D NAND effective device density. In this discussion, we will analyze various patterning schemes for staircase and slit structures at different TCAT (Terabit Cell Array Transistor) 3D NAND nodes. We will compare these schemes to understand their impact on effective transistor density. The schemes and data used in this study are based upon (or inferred from) tear down reports published by TechInsights®. Variations in patterning schemes, and the resulting virtual structures, were modeled using the SEMulator3D® semiconductor platform. read more…

2020 SPIE Advanced Lithography Conference – San Jose, CA – February 23-27, 2020

See us at booth #323/325!

 

Coventor Adds Process Optimization Features to SEMulator3D 8.0

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Coventor Adds Process Optimization Features to SEMulator3D® 8.0

New Features Enable SEMulator3D 8.0 to Address Both Process Modeling and Device Analysis for Better Insight into Advanced Semiconductor Technology Development

New in SEMulator3D 8.0, powerful new process simulation and analytics capabilities accelerate semiconductor technology development and Design-Technology Co-Optimization (DTCO).

New in SEMulator3D 8.0, powerful new process simulation and analytics capabilities accelerate semiconductor technology development and Design-Technology Co-Optimization (DTCO).

read more…

Video: “Scaling technology nodes without moving to new transistor architectures”

David Fried, vice president of computational products at Lam Research, looks at shrinking tolerances at advanced processes, how that affects variation in semiconductor manufacturing, and what can be done to achieve the benefits of scaling without moving to new transistor architectures.


[Video Attribution: Semiconductor Engineering] read more…

IEDM 2019 – San Francisco, CA – December 7-11, 2019

Coventor is exhibiting!

APC Conference 2019 – San Antonio, TX – October 28-31, 2019

Lam is a sponsor! Coventor will be giving the following talk:

  • Technology Node Scaling Through Variation Control

 

SEMICON West 2019 – San Francisco, CA – July 9-11, 2019

See us at booth #2239!

 

Coventor/Lam will also be will be giving the following talks: