January 29, 2020
Fig. 1 (a) DRAM Memory Cell, (b) GIDL in Cell Transistor, (c) Dielectric leakage between BLC and SNC, (d) Dielectric leakage at DRAM Capacitor
Published by Tae Yeon Oh at January 29, 2020
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Identifying DRAM Failures Caused by Leakage Current and Parasitic Capacitance

Leakage current has been a leading cause of device failure in DRAM design, starting with the 20nm technology node. Problems with leakage current in DRAM design can lead to reliability […]
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