3D printing has become all the rage in many areas, from home hobbyists to high-end industrial applications. The convenience, flexibility, functionality and decreasing price for printing things in 3D makes it an appealing tool for a wide range of purposes. So we thought we’d put it to use for demonstrating how virtual fabrication can help engineers understand the technical nuances of advanced process technologies – as well as show off a cool feature of our SEMulator3D tool.
At the recent SPIE Advanced Lithography Conference in San Jose, we unveiled a 3D printed model of a 16nm FinFET SRAM half-cell. We created the model using the mesh export capability in SEMulator3D, which supports surface meshes that are used in 3D printing as well. We used a standard third-party 3D printing service to print the model.
We’ve recently been getting a lot of customer requests to support 3D printing. The model caught the eye of many booth visitors — some of them had previously hand-made their own models using plasticine, Play-Doh, or rigid plastic (with pieces glued together), but not with this amount of detail or realism. It’s quite effective for educational or visualization purposes: hand-sized models of a company’s final product can be used to train or teach employees, or it is helpful for communicating with management or customers. Since the actual devices (ICs or MEMS) are extremely small these days (nanometer/micron scale), it can be easier for engineers to understand a device by using a larger physical model. The realistic physical model is very helpful for understanding how FinFETs are supposed to operate in three dimensions, since it is difficult to draw and visualize (in comparison with the 2D view of planar CMOS).
The printed model was also good way to demonstrate the mesh export capability in SEMulator3D, since many engineers don’t always know we have this function. Surface and volume meshes can be generated from SEMulator3D models and ported into other tools for further analyses or modeling. It’s also a great way to take advantage of the increasing accessibility and capabilities of 3D printing. So even though we are big believers in the efficiency of ‘virtual’ fabrication, there’s a lot of benefit to having a physical representation of a new technology, too.
Figure 1: A virtual model of a GAA FET showing residual SiGe after the channel release step. Process engineers have to make a trade-off between silicon loss and residual SiGe.(b) Variation in residual SiGe as a function of the channel width and etch lateral ratio. The higher the channel width, the higher the lateral ratio needed to etch away all the SiGe. Channel widths are shown as delta values from the nominal value of 30 nm.